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K4H560438H
K4H560838H
K4H561638H
www.DataSheet4U.com
DDR SDRAM
256Mb H-die DDR SDRAM Specification
66 TSOP-II with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 January 2006

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K4H560438H
K4H560838H
K4H561638H
Table of Contents
DDR SDRAM
1.0 Key Features .............................................................................................................................. 4
2.0 Ordering Information ................................................................................................................ 4
3.0 Operating Frequencies............................................................................................................... 4
4.0 Pin Description .......................................................................................................................... 5
5.0 Package Physical Dimension ................................................................................................... 6
6.0 Block Diagram (16Mbit x4 / 8Mbit x8 / 4Mbit x16 I/O x4 Banks).............................................. 7
7.0 Input/Output Function Description ........................................................................................... 8
8.0 Command Truth Table ............................................................................................................... 9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ............................................................................. 17
21.0 Component Notes ................................................................................................................... 18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.2 January 2006

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K4H560438H
K4H560838H
K4H561638H
Revision History
Revision
0.0
0.1
1.0
1.1
Month
July
August
November
February
Year
2005
2005
2005
2006
1.2
January
2007
DDR SDRAM
History
- First version for internal review
- Deleted x4 DDR333 speed.
- Revision 1.0
- Updated overshoot/undershoot specification & input slew rate for DDR333/400 speed
- Revised overshoot/undershoot specification following JEDEC SPEC
- Added tPDEX on AC parameter specification
Rev. 1.2 January 2006

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K4H560438H
K4H560838H
K4H561638H
DDR SDRAM
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
RoHS compliant
2.0 Ordering Information
Part No.
K4H560438H-UC/LA2
K4H560438H-UC/LB0
K4H560838H-UC/LCC
K4H560838H-UC/LB3
K4H560838H-UC/LA2
K4H560838H-UC/LB0
K4H561638H-UC/LCC
K4H561638H-UC/LB3
K4H561638H-UC/LA2
K4H561638H-UC/LB0
Org.
64M x 4
32M x 8
16M x 16
Max Freq.
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
SSTL2
66pin TSOP II
3.0 Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 1.2 January 2006

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K4H560438H
K4H560838H
K4H561638H
4.0 Pin Description
16Mb x 16
32Mb x 8
64Mb x 4
DDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66Pin TSOPII 57
11 (400mil x 875mil) 56
12 (0.65mm Pin Pitch) 55
13 54
14
15
Bank Address
BA0~BA1
16
53
52
51
17
18
19
Auto Precharge
A10
50
49
48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
256Mb TSOP-II Package Pinout
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.2 January 2006