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Preliminary Technical Data
FEATURES
8-bit analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green pulse filter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9983A is a complete 8-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p as well as graphics resolutions up to UXGA
(1600 x 1200 at 60 Hz).
The AD9983A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9983A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
High Performance
8-Bit Display Interface
AD9983A
FUNCTIONAL BLOCK DIAGRAM
AD9983A
8 AUTO OFFSET
Pr/REDIN1
Pr/REDIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8 AUTO OFFSET
Y/GREENIN1
Y/GREENIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8 AUTO OFFSET
Pb/BLUEIN1
Pb/BLUEIN0
2:1
MUX
CLAMP
AUTO GAIN
PGA
8-BIT
ADC
8 Cb/Cr/REDOUT
8
Y/GREENOUT
8
Cb/BLUEOUT
HSYNC1
HSYNC0
VSYNC0
VSYNC1
SOGIN1
SOGIN0
EXTCK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
DATACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFLO
Figure 1.
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The auto channel-
to-channel gain matching feature can be enabled to minimize
any gain mismatches between the three channels.
The AD9983A also offers full sync processing for composite
sync and sync-on-green applications. A clamp signal is
generated internally or may be provided by the user through the
CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9983A is
provided in a space-saving 80-lead, Pb-free, LQFP surface-
mount plastic package or a 64-lead LFCSP package, and is
specified over the 0°C to 70°C temperature range.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.

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AD9983A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Specifications..................................................................................... 3
Analog Interface Characteristics ................................................ 3
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels ........................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Theory of Operation ...................................................................... 11
Digital Inputs .............................................................................. 11
Analog Input Signal Handling.................................................. 11
Hsync and Vsync Inputs............................................................ 11
Serial Control Port ..................................................................... 11
Output Signal Handling............................................................. 11
Clamping ..................................................................................... 11
Gain and Offset Control............................................................ 12
Sync-on-Green............................................................................ 13
Reference Bypassing................................................................... 13
Clock Generation ....................................................................... 14
Sync Processing........................................................................... 16
Power Management.................................................................... 19
Timing Diagrams........................................................................ 19
Hsync Timing ............................................................................. 20
Coast Timing............................................................................... 21
Output Formatter ....................................................................... 21
Preliminary Technical Data
2-Wire Serial Control Port ............................................................ 22
Data Transfer via Serial Interface............................................. 22
2-Wire Serial Register Map ........................................................... 24
2-Wire Serial Control Registers.................................................... 30
Chip Identification ..................................................................... 30
PLL Divider Control .................................................................. 30
Clock Generator Control .......................................................... 30
Phase Adjust................................................................................ 30
Input Gain ................................................................................... 31
Input Offset ................................................................................. 31
Hsync Controls ........................................................................... 31
Vsync Controls ........................................................................... 32
Coast and Clamp Controls........................................................ 33
SOG Control ............................................................................... 34
Input and Power Control........................................................... 35
Output Control ........................................................................... 36
Sync Processing .......................................................................... 37
Detection Status.......................................................................... 37
Polarity Status ............................................................................. 38
Hsync Count ............................................................................... 38
Test Registers............................................................................... 38
PCB Layout Recommendations.................................................... 40
Analog Interface Inputs ............................................................. 40
Outputs (Both Data and Clocks).............................................. 41
Digital Inputs .............................................................................. 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
Rev. PrA | Page 2 of 44

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Preliminary Technical Data
AD9983A
SPECIFICATIONS
ANALOG INTERFACE CHARACTERISTICS
VD = 1.8 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C.
Table 1.
Parameter
RESOLUTION
Number of bits
LSB Size
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes2
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Full-Scale Matching
Offset Adjustment Range
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock to Data Skew tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
Maximum PLL Clock Rate
Minimum PLL Clock Rate
Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Temp
Test
Level
1
AD9983AKSTZ-140
AD9983AKCPZ-140
Min Typ Max
8
0.391
25°C I
Full VI
25°C I
Full VI
Full VI
±0.8
±1.0
AD9983AKSTZ-170
AD9983AKCPZ-170
Min Typ
Max
Unit
8
0.391
Bits
% of Full Scale
±0.9
±1.0
+2.25/−1.8
+2.65/−3.0
+2.5/−2.0
LSB
LSB
LSB
LSB
Full VI
Full VI
25°C V
25°C IV
Full IV
Full VI
Full VI
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
VI
IV
IV
IV
IV
Full
Full
Full
Full
25°C
VI
VI
V
V
V
0.5
1.0
125
1
1
1
50
140
10
−0.5 2.0
4.7
4.0
0
4.7
4.0
250
4.7
4.0
140
10
1.0
170
−0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
170
15
1.0
2
1.0
0.8
−1.0
1.0
125
1
50
7003
15
2
0.5 V p–p
V p–p
ppm/°C
1 μA
1 μA
% FS
% FS
MSPS
10 MSPS
2.0 ns
μs
μs
μs
μs
μs
ns
μs
μs
MHz
10 MHz
pS p-p
9253 pS p-p
pS/°C
V
0.8 V
−1.0 μA
1.0 μA
pF
Rev. PrA | Page 3 of 44

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AD9983A
Preliminary Technical Data
Parameter
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle, DATACK
Output Coding
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
DAVDD Supply Voltage
VD Supply Current (ID)
VDD Supply Current (IDD)
PVD Supply Current (IPVD)
DAVDD Supply Current (IDAVDD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Crosstalk
Temp
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
Full
Test
Level
1
VI
VI
IV
IV
IV
IV
IV
V
V
V
V
VI
VI
VI
V
V
AD9983AKSTZ-140
AD9983AKCPZ-140
Min Typ Max
VDD − 0.1
45 50
Binary
0.1
55
1.7 1.8 1.9
1.7 3.3 3.47
1.7 1.8 1.9
1.7 1.8 1.9
250
31
9
16
710
10
18
300
60
1 See the Explanation of Test Levels section.
2 Guaranteed by design, not production tested.
3 Jitter measurements taken at UXGA with recommended PLL settings.
AD9983AKSTZ-170
AD9983AKCPZ-170
Min Typ
Max
VDD − 0.1
45 50
Binary
0.1
55
1.755
1.7
1.7
1.7
1.8
3.3
1.8
1.8
255
34
9
19
10
18
1.9
3.47
1.9
1.9
740
300
60
Unit
V
V
%
V
V
V
V
mA
mA
mA
mA
mW
mA
mW
MHz
dBc
Rev. PrA | Page 4 of 44

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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VD
VDD
PVD
DAVDD
Analog Inputs
REFHI
REFLO
Digital Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
Rating
1.98 V
3.6 V
1.98 V
1.98 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to + 85°C
−65°C to + 150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9983A
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θJA θJC Unit
80-lead LQFP
35 16 °C/W
64-lead LFCSP
35 16 °C/W
ESD CAUTION
Rev. PrA | Page 5 of 44