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14-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
Preliminary Technical Data
AD9784
FEATURES
14-bit resolution, 200 MSPS input data rate
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
SFDR: 90 dBc @10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.75 LSB
INL = ±1.5 LSB
3.3 V compatible digital Interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Digital quadrature modulation architectures
Multicarrier WCDMA, GSM, TDMA, DCS,
PCS, CDMA Systems
PRODUCT DESCRIPTION
The AD9784 is a 14-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for com-
munications applications. It offers state of the art distortion and
noise performance. The AD9784 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9784 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9784 is
manufactured on an advanced low cost 0.25 µm CMOS process.
P1B[15:0]
P2B[15:0]
DATACLK/
PLL_LOCK
FUNCTIONAL BLOCK DIAGRAM
LATCH
×1
LATCH
2× 2× 2×
I
fDAC/2
fDAC/4
fDAC/8
0
90
×2
×4
×8
Q
0
90
0
90
t
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
LPF
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. PrC
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Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

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AD9784
TABLE OF CONTENTS
Product Highlights ........................................................................... 3
AD9784–Specifications.................................................................... 4
DC Specifications ......................................................................... 4
Dynamic Specifications ............................................................... 5
Digital Specifications ................................................................... 6
Pin Configuration and Function Descriptions............................. 7
Clock .............................................................................................. 7
Analog............................................................................................ 8
Data ................................................................................................ 8
Serial Interface .............................................................................. 9
Definitions of Specifications ......................................................... 10
Typical Performance Charatceristics ........................................... 12
Serial Control Interface.................................................................. 17
General Operation of the Serial Interface ............................... 17
Instruction Byte .......................................................................... 17
Serial Interface Port Pin Descriptions ..................................... 17
MSB/LSB Transfers..................................................................... 18
Notes on Serial Port Operation ................................................ 18
Mode Control (via SPI Port) ......................................................... 19
REVISION HISTORY
Revision PrC: Preliminary Version
Preliminary Technical Data
Digital Filter Specifications ........................................................... 23
Digital Interpolation Filter Coefficients.................................. 23
AD9784 Clock/Data Timing..................................................... 24
Interpolation Modes .................................................................. 27
Real and Complex Signals......................................................... 28
Modulation Modes..................................................................... 29
Power Dissipation ...................................................................... 34
Dual Channel Complex Modulation with Hilbert ................ 35
Hilbert Transform Implementation......................................... 36
Operating the AD9784 Rev E Evaluation Board........................ 40
Power Supplies............................................................................ 40
PECL Clock Driver .................................................................... 40
Data Inputs.................................................................................. 41
SPI Port ........................................................................................ 41
Operating with PLL Disabled ................................................... 41
Operating with PLL Enabled .................................................... 42
Analog Output ............................................................................ 42
Outline Dimensions ....................................................................... 52
ESD Caution................................................................................ 52
Rev. PrC | Page 2 of 52

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Preliminary Technical Data
PRODUCT HIGHLIGHTS
1. The AD9784 is a member of a high speed interpolating
TxDAC+ family with 16-/14-/12-bit resolutions.
2. 2×/4×/8× user selectable interpolating filter eases data rate
and output signal reconstruction filter requirements.
3. 200 MSPS input data rate.
4. Ultrahigh speed 500 MSPS DAC conversion rate.
5. Internal PLL/clock divider provides data rate clock for easy
interfacing.
AD9784
6. Flexible clock with single-ended or differential input:
CMOS, 1 V p-p sine wave and LVPECL capability.
7. Complete CMOS DAC function operates from a 2.7 V to
3.6 V single analog (AVDD) supply and a 2.5 V (DVDD)
digital supply. The DAC full-scale current can be reduced
for lower power operation, and a sleep mode is provided
for low-power idle periods.
8. On-chip voltage reference: The AD9784 includes a 1.20 V
temperature-compensated band gap voltage reference.
Rev. PrC | Page 3 of 52

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AD9784
Preliminary Technical Data
AD9784–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA, unless
otherwise noted
Parameter
Min Typ Max
Unit
RESOLUTION
DC Accuracy1
14 Bits
Integral Nonlinearity
1.5 LSB
Differential Nonlinearity
0.75 LSB
ANALOG OUTPUT
Offset Error
% of FSR
Gain Error (Without Internal Reference)
% of FSR
Gain Error (With Internal Reference)
Full-Scale Output Current2
% of FSR
10 20 mA
Output Compliance Range
–1.0 +1.0 V
Output Resistance
TBD kΩ
Output Capacitance
3 pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14 1.20 1.26
1
V
µA
REFERENCE INPUT
Input Compliance Range
0.1 1.25 V
Reference Input Resistance (Ext Reference Mode)
10 MΩ
Small Signal Bandwith
0.5 MHz
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
ppm of FSR/°C
Gain Drift (Without Internal Reference)
ppm of FSR/°C
Gain Drift (With Internal Reference)
ppm of FSR/°C
Reference Voltage Drift
ppm /°C
POWER SUPPLY
AVDD1, AVDD2
Voltage Range
3.1 3.3 3.5
V
Analog Supply Current (IAVDD1)
Analog Supply Current (IAVDD2)
IAVDD1 in SLEEP Mode
ACVDD, ADVDD
mA
mA
mA
Voltage Range
2.35 2.5 2.65 V
Analog Supply Current (IACVDD)
Analog Supply Current (IADVDD)
CLKVDD
mA
mA
Voltage Range
2.35 2.5 2.65 V
Clock Supply Current (ICLKVDD)
DVDD
mA
Voltage Range
2.35 2.5 2.65 V
Digital Supply Current (IDVDD)
DRVDD
mA
Voltage Range
2.35 2.5/3.3 3.5
V
Digital Supply Current (IDRVDD)
Nominal Power Dissipation4
mA
1.25 W
OPERATING RANGE
–40 +85 °C
1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 Use an external amplifier to drive any external load.
4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× Interpolation, fDAC/4 Modulation, Hilbert Off.
Rev. PrC | Page 4 of 52

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Preliminary Technical Data
AD9784
DYNAMIC SPECIFICATIONS
Table 2. TMIN to TMAX, AVDD1, AVDD2 = 3.3 V, ACVDD, ADVDD, CLKVDD, DVDD, DRVDD = 2.5 V, IOUTFS = 20 mA,
Differential Transformer Coupled Output, 50 Ω Doubly Terminated, unless otherwise noted
Parameter
Min Typ Max
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (fDAC)
500
Output Settling Time (tST) (to 0.025%)
Output Propogation Delay5 (tPD)
Output Rise Time (10%–90%)6
Output Fall Time (90%–10%)6
Output Noise (IOUTFS = 20 mA)
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 160 MSPS; fOUT= 1 MHz
95
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
fDATA = MSPS; fOUT = MHz
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS)
fDATA = 160 MSPS; fOUT1 = 25 MHz; fOUT2 = 31 MHz
80
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
fDATA = MSPS; fOUT1 = MHz; fOUT2 = MHz
Total Harmonic Distortion (THD)
fDATA = MSPS; fOUT = MHz; 0 dBFS
fDATA = MSPS; fOUT = MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
fDATA = MSPS; fOUT = MHz; 0 dBFS
fDATA = MSPS; fOUT = MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
WCDMA with MHz BW, MHz Channel Spacing
IF = 16 MHz, fDATA = 65.536 MSPS
IF = 32 MHz, fDATA = 131.072 MSPS
Four-Tone Intermodulation
MHz, MHz, MHz and MHz at –12 dBFS (fDATA = MSPS, Missing Center)
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = MHz
MHz, MHz, MHz and MHz at dBFS
fDATA = MSPS, fDAC = MHz
Unit
MSPS
ns
ns
ns
ns
pA√Hz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dBFS
dBFS
dBc
dBc
dBFS
dBFS
5 Propagation delay is delay from CLK input to DAC update.
6 Measured single-ended into 50 Ω load.
Rev. PrC | Page 5 of 52