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March 1997
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CDP1883,
CDP1883C
CMOS 7-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder Func-
tions Multiplexed or Non-Multiplexed
• Interfaces Directly with the CDP1800-Series Micropro-
cessors
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
5V 10V
CDP1883CE CDP1883E
TEMP.
RANGE
-40oC to
+85oC
PKG.
PACKAGE NO.
PDIP
E20.3
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to VDD,
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
Pinout
CDP1883, CDP1883C
(PDIP)
TOP VIEW
CLOCK 1
MA0 2
MA1 3
MA2 4
MA3 5
MA4 6
MA5 7
MA6 8
CE 9
VSS 10
20 VDD
19 A8
18 A9
17 A10
16 A11
15 A12
14 CS0
13 CS1
12 CS2
11 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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CDP1883, CDP1883C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1883C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW
Operating Temperature
Package Type E . . . .
Range
......
(TA)
....
.
.
.
.
.
.
.
.
.
.
.
.
.-40oC
to
+85oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera-
tion of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
CDP1883
CDP1883C
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
DC Operating Voltage Range
Input Voltage Range
4 10.5 4
6.5 V
VSS
VDD
VSS
VDD
V
Static Electrical Specifications At TA = -40oC to +85oC, VDD ± 5%, Except as Noted:
CONDITIONS
CDP1883
CDP1883C
PARAMETER
SYMBOL
VO
(V)
VIN VDD
(NOTE 1)
(NOTE 1)
(V) (V) MIN TYP MAX MIN TYP MAX UNITS
Quiescent Device
Current
IDD - 0, 5 5 -
1 10 -
-
0, 10
10
-
10 100 -
5 50 µA
- - µA
Output Low Drive
(Sink) Current
IOL 0.4 0, 5 5 1.6 3.2
0.5 0, 10 10
3.2
6.4
- 1.6 3.2
--
-
- mA
- mA
Output High Drive
(Source) Current
IOH
4.6 0, 5
5
-1.15
-2.3
9.5 0, 10 10 -2.3 -4.6
- -1.15 -2.3
--
-
- mA
- mA
Output Voltage
Low-Level (Note 2)
VOL - 0, 5 5 -
-
0, 10
10
-
0 0.1 -
0 0.1 -
0 0.1 V
- -V
Output Voltage
High-Level (Note 2)
VOH
- 0, 5 5 4.9
5
-
0, 10
10
9.9
10
- 4.9
--
5
-
-V
-V
Input Low Voltage
VIL 0.5, 4.5 - 5 -
0.5, 9.5
-
10 -
- 1.5 -
- 3-
- 1.5 V
- -V
Input High Voltage
VIH 0.5, 4.5
0.5, 9.5
-
-
5 3.5
10 7
-
-
- 3.5
--
-
-
-V
-V
Input Leakage Current
IIN
Any
Input
0, 5
0, 10
5
10
-
-
- ±1 -
- ±2 -
- ±1 µA
- - µA
Operating Current
(Note 3)
IDD1
0, 5
0, 10
0, 5
0, 10
5
10
-
-
- 2-
- 4-
- 2 mA
- - mA
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CDP1883, CDP1883C
Static Electrical Specifications At TA = -40oC to +85oC, VDD ± 5%, Except as Noted: (Continued)
CONDITIONS
CDP1883
CDP1883C
PARAMETER
SYMBOL
VO
(V)
VIN VDD
(NOTE 1)
(NOTE 1)
(V) (V) MIN TYP MAX MIN TYP MAX UNITS
Minimum Data
Retention Voltage
VDR
VDD = VDR
- 2 2.4 - 2 2.4 V
Data Retention Current IDR
VDD = 2.4V
- 0.01 1 -
0.5
Input Capacitance
CIN - - - - 5 7.5 - 5
Output Capacitance
COUT
-
-
-
-
10 15 -
10
NOTES:
1. Typical values are for TA = +25oC.
2. IOL = IOH = µA
3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuit.
5 µA
7.5 pF
15 pF
Functional Diagram
MA0 2
MA1 3
MA2 4
MA3 5
MA4 6
MA5 7
MA6 8
CLOCK 1
CE 9
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
CQ
DQ
CQ
VDD = 20
VSS = 10
19 A8
18 A9
17 A10
16 A11
15 A12
14 CS0
13 CS1
12 CS2
11 CS3
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CDP1883, CDP1883C
Signal Descriptions/Pin Functions
TRUTH TABLE
CLOCK: Latch Input Control - a high on the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high-to-low transition of the clock input. This
pin is connected to TPA in CDP1800-series systems and tied
to VDD for other applications.
MA0 - MA4: Address inputs to the high-byte address
latches.
INPUTS
CE CLK MA0 - 4
X11
X10
X0X
OUTPUTS
A8 - A12
1
0
Previous State
MA5 - MA6: High byte address inputs decoded to produce
chip selects CS0 - CS3.
CE: CHIP ENABLE input - A low on this pin will enable the
chip select decoder. A high on this pin forces CS0, CS1,
CS2, and CS3 outputs to a high (false) state.
A8 - A12: Latched high-byte address outputs.
CS0 - CS3: One of four latched and decoded Chip Select
outputs.
VDD, VSS: Power and ground pins, respectively.
TRUTH TABLE
INPUTS
OUTPUTS
CE CLK MA5 MA6 CS0 CS1 CS2 CS3
01000111
01101011
01011101
01111110
X = Don’t Care
Application Information
The CDP1883 and CDP1883C can be interfaced, without
external components, with CDP1800-series microprocessor
systems. These microprocessors feature a multiplexed
address bus and provide an address latch signal (TPA) that
is used as the clock input of the CDP1883. See Figure 2 and
Figure 3.
This signal is used to latch 7 bits of the high-order address.
The lower five high-order address inputs are latched and
held to be used with the eight lower-order address inputs to
access an 8K x 8-bit memory. The two upper high-order
address inputs are latched and decoded for use as chip
selects.
The latched address and decoding functions of the
CDP1883 and CDP1883C allow them to operate with 32K-
byte memory systems. In addition, smaller memory systems
can be configured with 4K x 8-bit or smaller memories, or a
mix of memory sizes up to 8K x 8-bit.
0 0XX
Previous State
1XXX1 1 1 1
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
See Figure 1
CDP1883
CDP1883C
PARAMETER
VDD
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
(V) MIN TYP
MAX MIN TYP
MAX UNITS
Minimum Setup Time,
Memory Address to CLOCK
tMACL
5
-
10
35
-
10
35 ns
10 - 8 25 - -
- ns
Minimum Hold Time,
Memory Address After CLOCK
tCLMA
5
-
8
25 -
8
25 ns
10 - 8 25 - -
- ns
Minimum CLOCK Pulse Width
tCLCL
5
-
50
75
-
50
75 ns
10 - 25 40 -
-
- ns
PROPAGATION DELAY TIMES
Chip Enable to Chip Select
tCECS
5
-
75 150 -
75
150 ns
10 -
45 100 -
-
- ns
CLOCK to Chip Select
tCLCS
5
- 100 175 - 100 175 ns
10 -
65 125 -
-
- ns
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CDP1883, CDP1883C
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
See Figure 1 (Continued)
CDP1883
CDP1883C
PARAMETER
VDD
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
(V) MIN TYP
MAX MIN TYP
MAX UNITS
CLOCK to Address
tCLA 5 - 100 175 - 100 175 ns
10 -
65 125 -
-
- ns
Memory Address to Chip Select
tMACS
5
- 100 175 - 100 175 ns
10 -
75 125 -
-
- ns
Memory Address to Address
tMAA 5 - 80 125 - 80 125 ns
10 - 40 60 -
-
- ns
NOTES:
1. Typical values are for TA = 25oC.
2. Maximum limits of minimum characteristics are the values above which all devices function.
CE
CS0, CS1, CS2, CS3
VALID CHIP ENABLE
tCECS
tCECS
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MA0 - MA5
tMACL
CLOCK
tCLCL
CS0, CS1, CS2, CS3
tCLA
A8 - A12
tCLMA
tCLCS
tMACS
(B) MEMORY ADDRESS SETUP AND HOLD TIME
tMAA
tMAA
tMACS
FIGURE 1. CDP1883 TIMING WAVEFORMS
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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