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Data Sheet
655 MHz Low Jitter Clock Generator
AD9540
FEATURES
Excellent intrinsic jitter performance
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable phase/frequency profiles
400 MSPS internal DDS clock speed
48-bit frequency tuning word resolution
14-bit programmable phase offset
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant output driver
APPLICATIONS
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
Agile LO frequency synthesis
Automotive radar
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND CP_VDD
CP_RSET
REFIN
REFIN
SYNC_IN/STATUS
CLK1
CLK1
SCLK
SDI/O
SDO
CS
S2
S1
S0
SYNC, PLL
LOCK
M DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
CP
REF, AMP
CHARGE
PUMP
DIVIDER
1, 2, 4, 8
SERIAL
CONTROL
PORT
TIMING AND
CONTROL LOGIC
PHASE/
FREQUENCY
PROFILES
CML
CLK
DIVCLK
48
14
AD9540
DDS 10
DAC
CP_OUT
CLK2
CLK2
DRV_RSET
OUT0
OUT0
IOUT
IOUT
Figure 1.
DAC_RSET
Rev. B
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AD9540
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Overview............................................................................. 3
Specifications..................................................................................... 4
Loop Measurement Conditions.................................................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Typical Application Circuits.......................................................... 17
Application Circuit Descriptions ............................................. 18
Theory of Operation ...................................................................... 19
REVISION HISTORY
9/2016—Rev. A to Rev. B
Change to Features ........................................................................... 1
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
2/2006—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Applications Section .................................................... 1
Changes to Functional Block Diagram.......................................... 1
Changes to Table 1............................................................................ 4
Changes to Typical Application Circuits Section....................... 17
Updates to Ordering Guide........................................................... 32
7/2004—Revision 0: Initial Version
Data Sheet
PLL Circuitry .............................................................................. 19
CML Driver................................................................................. 19
DDS and DAC............................................................................. 20
Modes of Operation ....................................................................... 21
Selectable Clock Frequencies and Selectable Edge Delay ..... 21
Synchronization Modes for Multiple Devices.............................. 21
Serial Port Operation ..................................................................... 22
Instruction Byte .......................................................................... 23
Serial Interface Port Pin Description....................................... 23
MSB/LSB Transfers .................................................................... 23
Register Map and Description ...................................................... 24
Control Register Bit Descriptions ............................................ 27
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
Rev. B | Page 2 of 32

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Data Sheet
PRODUCT OVERVIEW
The AD9540 is Analog Devices’ first dedicated clocking
product specifically designed to support the extremely stringent
clocking requirements of the highest performance data
converters. The device features high performance PLL (phase-
locked loop) circuitry, including a flexible 200 MHz phase
frequency detector and a digitally controlled charge pump
current. The device also provides a low jitter, 655 MHz CML-
mode, PECL-compliant output driver with programmable slew
rates. External VCO rates up to 2.7 GHz are supported.
AD9540
Extremely fine tuning resolution (steps less than 2.33 µHz) is
another feature supported by this device. Information is loaded
into the AD9540 via a serial I/O port that has a device write
speed of 25 Mbps. The AD9540 frequency divider block can
also be programmed to support a spread spectrum mode of
operation.
The AD9540 is specified to operate over the extended
automotive range of −40°C to +85°C.
Rev. B | Page 3 of 32

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AD9540
Data Sheet
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C), DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter
TOTAL SYSTEM JITTER AND PHASE NOISE FOR
105 MHz ADC CLOCK GENERATION CIRCUIT
Converter Limiting Jitter1
Resultant Signal-to-Noise Ratio (SNR)
Phase Noise of Fundamental
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
≥1 MHz Offset
TOTAL SYSTEM PHASE NOISE FOR 210 MHz
ADC CLOCK GENERATION CIRCUIT
Phase Noise of Fundamental
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
TOTAL SYSTEM TIME JITTER FOR CLOCKS
155.52 MHz Clock
622.08 MHz Clock
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
FIN = 414.72 MHz, FOUT = 51.84 MHz
FIN = 1244.16 MHz, FOUT = 155.52 MHz
FIN = 2488.32 MHz, FOUT = 622.08 MHz
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
FIN = 81.92 MHz, FOUT = 10.24 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
≥1 MHz
FIN = 983.04 MHz, FOUT = 122.88 MHz
@ 10 Hz
@ 100 Hz
@ 1 KHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
Min
Typ Max
720
59.07
80
92
101
110
147
153
79.2
86
95
105
144
151
581
188
136
101
108
120
128
137
145
150
153
115
125
132
142
146
151
153
Unit
fS rms
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fS rms
fS rms
fS rms
fS rms
fS rms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
12 kHz to 1.3 MHz bandwidth
12 kHz to 5 MHz bandwidth
R = 8, BW = 12 kHz to 400 kHz
R = 8, BW = 12 kHz to 1.3 MHz
R = 4, BW = 12 kHz to 5 MHz
RF Divider R = 8
RF Divider R = 8
Rev. B | Page 4 of 32

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Data Sheet
Parameter
FIN = 1966.08 MHz, FOUT = 491.52 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
FIN = 2488 MHz, FOUT = 622 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
≥3 MHz
PHASE FREQUENCY DETECTOR/CHARGE PUMP
REFIN Input
Input Frequency2
÷M Set to Divide by at Least 4
÷M Bypassed
Input Voltage Levels
Input Capacitance
Input Resistance
CLK2 Input
Input Frequency
÷N Set to Divide by at Least 4
÷N Bypassed
Input Voltage Levels
Input Capacitance
Input Resistance
Charge Pump Source/Sink Maximum Current
Charge Pump Source/Sink Accuracy
Charge Pump Source/Sink Matching
Charge Pump Output Compliance Range3
STATUS Drive Strength
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 100 MHz PFD Frequency
@ 200 MHz PFD Frequency
RF DIVIDER (CLK1 ) INPUT SECTION (÷R)
RF Divider Input Range
Min
200
200
0.5
1
Input Capacitance (DC)
Input Impedance (DC)
Input Duty Cycle
Input Power/Sensitivity
Input Voltage Level
42
−10
200
Typ Max
105
112
122
130
141
144
146
100
108
115
125
135
140
142
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
AD9540
Test Conditions/Comments
RF Divider R = 4
RF Divider R = 4
450
1500
655
200
600
10
MHz
MHz
mV p-p
pF
450
1500
2
655
200
600
10
4
5
2
CP_VDD − 0.5
MHz
MHz
mV p-p
pF
mA
%
%
V
mA
148 dBc/Hz
133 dBc/Hz
116 dBc/Hz
113 dBc/Hz
2700
3
1500
50
58
+4
1000
MHz
pF
%
dBm
mV p-p
DDS SYSCLK not to
exceed 400 MSPS
Single-ended, into a 50 Ω load4
Rev. B | Page 5 of 32