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UNISONIC TECHNOLOGIES CO., LTD
4066
QUAD BILATERAL SWITCH
CMOS IC
DESCRIPTION
The UTC 4066 is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals.
FEATURES
* Wide supply voltage range: 3V ~ 15V.
* High noise immunity : 0.45VDD (typ.)
* Wide range of digital and ± 7.5VPEAK analog switching
* “ON” resistance for 15V operation : 80
* Matched ”ON” resistance : RON=5(typ.)
over 15V signal input
* “ON” resistance flat over peak-to-peak signal range
* High “ON” / “OFF” : 65 dB (typ.)
output voltage ratio @ fIS=10kHz, RL=10k
* High degree linearity: 0.1% distortion (typ.).
@ fIS=1kHz, VIS=5Vp-p.
* VDD-VSS=10V, RL=10k
* Extremely low ”OFF” : 0.1nA (typ.)
* switch leakage @VDD-VSS=10V, Ta=25
* Extremely high control input impedance : 1012(typ.)www.DataSheet4U.com
* Low crosstalk : -50dB (typ.)
* between switches @ fIS=0.9MHz, RL=1k
* Frequency response, switch ”ON” : 40MHz (typ.)
ORDERING INFORMATION
Ordering Number
Normal
Lead Free Plating
4066-D14-T
4066L-D14-T
4066-S14-R
4066L-S14-R
4066-S14-T
4066L-S14-T
4066-P14-R
4066L-P14-R
4066-P14-T
4066L-P14-T
Package
DIP-14
SOP-14
SOP-14
TSSOP-14
TSSOP-14
SOP-14
DIP-14
TSSOP-14
*Pb-free plating product number: 4066L
Packing
Tube
Tape Reel
Tube
Tape Reel
Tube
4066L-D14-T
(1)Packing Type
(2)Package Type
(3)Lead Plating
(1) R: Tape Reel, T: Tube
(2) D14: DIP-14, S14: SOP-14, P14: TSSOP-14
(3) L: Lead Free Plating, Blank: Pb/Sn
www.unisonic.com.tw
Copyright © 2005 Unisonic Technologies Co., Ltd
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4066
PIN CONFIGURATION
IN / OUT 1
OUT/IN 2
OUT/IN 3
IN / OUT 4
CONTROL B 5
CONTROL C 6
Vss 7
SW A
SW D
SW B
SW C
14 VDD
13 CONTROL A
12 CONTROL D
11 IN/ OUT
10 OUT/IN
9 OUT/IN
8 IN /OUT
CMOS IC
SCHEMATIC DIAGRAM
IN/ OUT
CONTROL
OUT/ IN
Vss
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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4066
CMOS IC
ABSOLUTE MAXIMUM RATINGS (VSS=0V, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VDD -0.5 ~ +18
V
Input Voltage
DIP-14
VIN
-0.5 ~ Vcc+0.5
700
V
mW
Power Dissipation
SOP-14
PD
500
mW
TSSOP-14
500 mW
Junction Temperature
TJ +125 °C
Storage Temperature
TSTG
-40 ~ +150
°C
Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS (VSS=0V, unless otherwise specified)
PARAMETER
Supply Voltage
Input Voltage
Operating Temperature Range
SYMBOL
VDD
VIN
TOPR
RATINGS
3 ~ 15
0 ~ VDD
-40 ~ +85
UNIT
V
V
°C
DC ELECTRICAL CHARACTERISTICS (VSS=0V, unless otherwise specified)
PARAMETER SYMBOL
CONDITIONS
Quiescent Device
Current
IDD
VDD=5V
VDD=10V
VDD=15V
SIGNAL INPUTS AND OUTPUTS
Input or Output
Leakage
Switch “OFF”
IIS Vc=0
“ON” Resistance
RL=10k~ (VDD-VSS/2)
Vc=VDD, VSS ~ VDD
RON VDD=5V
VDD=10V
VDD=15V
”ON” Resistance
Between Any 2 of 4
Switches
RON
RL=10k~ (VDD-VSS/2)
Vc=VDD, VIS=VSS ~VDD
VDD=10V
VDD=15V
CONTROL INPUTS
Low Level Input
Voltage
HIGH Level Input
Voltage
VILC
VIHC
VIS= VSS and VDD
Vos=VDD and VSS
IIS= ±10µA
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V (Note 4)
VDD=15V
Input Current
VDD-VSS=15V
IIN VDD VIS VSS
VDD Vc VSS
-40°C
MIN MAX
MIN
+25°C
TYP
MAX
+85°C
MIN MAX
UNITS
1.0 0.01 1.0
7.5 µA
2.0 0.01 2.0
15 µA
4.0 0.01 4.0
30 µA
±50
±0.1 ±50
±200 nA
850
270 1050
1200
330 120 400 520
210
80 240
300
10
5
1.5 2.25
3.0 4.5
4.0 6.75
3.5 3.5 2.75
7.0 7.0 5.5
11.0 11.0 8.25
1.5
3.0
4.0
3.5
7.0
11.0
1.5
3.0
4.0
±0.3
±10-5 ±0.3
±1.0
V
V
V
V
V
V
µA
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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4066
CMOS IC
AC ELECTRICAL CHARACTERISTICS (AC Parameters are guaranteed by DC correlated testing)
(Ta=25 , tr=tf=20 ns and Vss=0V unless otherwise)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Propagation Delay Time Signal
Input to Signal Output
Propagation Delay Time
Control Input to Signal
Output High Impedance to
TPHL, TPLH
tPZH, tPLZ
Vc=VDD, CL=50pF, (Figure1)
RL=200k
RL=1.0k, CL=50pF
(Figure 2, Figure3)
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
25 55
15 35
10 25
125
60
ns
ns
ns
ns
ns
Logical Level
VDD=15V
50 ns
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response -Switch
“ON” (Frequency at-3dB)
tPHZ, tPLZ
RL=1.0k, CL=50pF, (Figure 2, Figure3)
VDD=5V
VDD=10V
VDD=15V
Vc=VDD=5V, Vss= -5V
RL=10k, VIS=5VP-P, f=1kHz, (Figure 4)
Vc=VDD=5V, Vss= -5V
RL=1k, VIS=5Vp-p
20 Log10 VOS/VOS (1kHz)-dB
(Figure 4)
125
60
50
0.1
ns
ns
ns
%
40 MHz
Feedthrough - Switch “OFF”
(Frequency at –50 dB)
Crosstalk Between Any Two
Switches(Frequency at-50dB)
Crosstalk; Control Input to
Signal Output
VDD=5.0V, Vcc=Vss= -5.0V,
RL=1k, VIS=5.0VP-P, 20Log10,
VOS/VIS= -50dB, (Figure 4)
VDD=VC(A)=5.0V; Vss=Vc (B)=5.0V,
RL=1k, VIS(A)=5.0VP-P, 20Log10,
VOS(B)/VIS (A)= -50dB (Figure 5)
VDD=10V, RL=10k, RIN=1.0k
Vcc=10V Square Wave, CL=50pF
(Figure 6)
1.25
0.9
150
MHz
mVp-p
Maximum Control Input
RL=1.0k, CL=50pF, (Figure 7)
Vos (f) =1/2Vos (1.0kHz)
VDD=5.0V
VDD=10V
VDD=15V
6.0 MHz
8.0 MHz
8.5 MHz
Signal Input Capacitance
CIS
8.0 pF
Signal Output Capacitance
COS
VDD=10V
8.0 pF
Feedthrough Capacitance
CIOS
VC=0V
0.5 pF
Control lnput Capacitance
CIN
5.0 7.5 pF
Note 1: These devices should not be connected to circuits with the power ”ON”
Note 2: In all cases, these is approximately 5pF of probe and jig capacitance in the output; however, this capacitance
is included in CL wherever it is specified.
Note 3: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. Vc is the voltage at the control
input.
Note 4: Conditions for VIHC: (a) VIS=VDD, Ios=standard B series IOH. (b) VIS=0V, IOL=standard B series IOL
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4066
CMOS IC
SPECIAL CONSIDERATIONS
In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability
should exceed VDD/RL (RL=effective external load of the UTC 4066 bilateral switches).This provision avoids any
permanent current flow or clamp action of the VDD supply when power is applied or removed from UTC 4066.
In certain applications, the external load-resistor current may include both VDD and Signal-line components. To
avoid drawing VDD current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the
bidirectional swith must not exceed 0.6V at Ta 25 , or 0.4V at Ta >25 (calculated from RON values shown).
NO VDD current will flow through RL if the switch current flows into terminals2, 3, 9 or 10.
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
VC=VDD
VIS
VDD
CONTROL
VDD
IN/OUT 1 OF 4 OOTUUT/I/NIN
SWITCHES
Vss
CL
50pF
VOS
RL
200 K
VDD
VIS
0V
VDD
VOS
0V
tf
90%
50%
10%
t PLN
50%
tf
t PNL
VC
VIS=VDD
FIGURE 1. t PHL, t PLH Propagation Delay Time Signal Input to Signal Output
VDD
t PZH
t PHZ
CONTROL VDD
1 OF 4
IN/OUT OUT/IN
SWITCHES
CL
VOS
RL
VDD
0V
VOH
50%
tPZH
VDD 50%
0V VDD
VOH
t PHZ
90%
Vss 50pF 1K
0V 10%
0V
VC
VIS=0V
FIGURE 2. tPZH, t PHZ Propagation Delay Time Control to Signal Output
VDD
CONTROL VDD
1OF 4
IN/OUT OUT/IN
SWITCHES
Vss
VDD
RL
1K
VOS
CL
50pF
VDD
t PZL
VDD
50%
0V tPZL 0V
VDD
90%
VDD
VOL
VOL
FIGURE 3 . t PZL, t PLZ Propagation Delay Time Control to Signal Output
t PLZ
50%
t PLZ
10%
VC 5V
CONTROL VDD
1OF 4
VIS IN/OUT OUT/IN
VOS
SWITCHES
Vss RL
-5V
Vc=VDD for distortion and frequency response tests
Vc= Vss for feedthrough test
2.5V
VIS = 0V
-2.5V
1/f
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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