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M
MCP6S21/2/6/8
Single-Ended, Rail-to-Rail I/O, Low Gain PGA
Features
Description
• Multiplexed Inputs: 1, 2, 6 or 8 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI™)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max)
• Low Offset: ±275 µV (max)
• High Bandwidth: 2 to 12 MHz (typ)
• Low Noise: 10 nV/Hz @ 10 kHz (typ)
• Low Supply Current: 1.0 mA (typ)
• Single Supply: 2.5V to 5.5V
Typical Applications
• A/D Converter Driver
• Multiplexed Analog Applications
• Data Acquisition
The Microchip Technology Inc. MCP6S21/2/6/8 are
analog Programmable Gain Amplifiers (PGA). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to eight chan-
nels through an SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single
supply applications needing flexible performance or
multiple inputs.
The one channel MCP6S21 and the two channel
MCP6S22 are available in 8-pin PDIP, SOIC and
MSOP packages. The six channel MCP6S26 is avail-
able in 14-pin PDIP, SOIC and TSSOP packages. The
eight channel MCP6S28 is available in 16-pin PDIP
and SOIC packages. All parts are fully specified from
-40°C to +85°C.
• Industrial Instrumentation
• Test Equipment
• Medical Instrumentation
Blockwww.DataSheet4U.com Diagram
VDD
Package Types
MCP6S21
PDIP, SOIC, MSOP
VOUT 1
8 VDD
CH0 2
7 SCK
VREF 3
VSS 4
6 SI
5 CS
MCP6S22
PDIP, SOIC, MSOP
VOUT 1
8 VDD
CH0 2
7 SCK
CH1 3
6 SI
VSS 4
5 CS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CS
SI
SO
SCK
MUX
SPI™
Logic
+
-
Gain 8
Switches
RF
RG
VOUT
MCP6S26
PDIP, SOIC, TSSOP
MCP6S28
PDIP, SOIC
VOUT 1
CH0 2
14 VDD VOUT 1
13 SCK CH0 2
16 VDD
15 SCK
CH1 3
12 SO CH1 3
14 SO
CH2 4
11 SI
CH2 4
13 SI
CH3 5
CH4 6
CH5 7
10 CS
9 VSS
8 VREF
CH3 5
CH4 6
CH5 7
CH6 8
12 CS
11 VSS
10 VREF
9 CH7
POR
VSS
VREF
2003 Microchip Technology Inc.
DS21117A-page 1

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MCP6S21/2/6/8
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All inputs and outputs....................... VSS - 0.3V to VDD +0.3V
Difference Input voltage ........................................ |VDD - VSS|
Output Short Circuit Current...................................continuous
Current at Input Pin .............................................................±2 mA
Current at Output and Supply Pins ................................ ±30 mA
Storage temperature .....................................-65°C to +150°C
Junction temperature .................................................. +150°C
ESD protection on all pins (HBM;MM).................. ≥ 2 kV; 200V
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
PIN FUNCTION TABLE
Name
VOUT
CH0-CH7
VSS
VDD
SCK
SI
SO
CS
VREF
Function
Analog Output
Analog Inputs
Negative Power Supply
Positive Power Supply
SPI Clock Input
SPI Serial Data Input
SPI Serial Data Output
SPI Chip Select
External Reference Pin
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, SI and SCK are tied low and CS is tied high.
Parameters
Sym Min Typ
Max Units
Conditions
Amplifier Input
Input Offset Voltage
Input Offset Voltage Drift
Power Supply Rejection Ratio
VOS
VOS/TA
PSRR
-275
70
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±4 —
85 —
µV
µV/°C
dB
G = +1, VDD = 4.0V
TA = -40 to +85°C
G = +1 (Note 1)
Input Bias Current
Input Bias Current over
Temperature
Input Impedance
Input Voltage Range
Amplifier Gain
IB
IB
ZIN
VIVR
— ±1
— — 250
— 1013||15
VSS0.3
VDD+0.3
pA
pA
||pF
V
CHx = VDD/2
TA = -40 to +85°C,
CHx = VDD/2
Nominal Gains
G
— 1 to 32
V/V +1, +2, +4, +5, +8, +10, +16 or +32
DC Gain Error
G = +1
G +2
DC Gain Drift
G = +1
G +2
Internal Resistance
Internal Resistance over
Temperature
Amplifier Output
gE
gE
G/TA
G/TA
RLAD
RLAD/TA
-0.1
-1.0
3.4
±0.0002
±0.0004
4.9
+0.028
+0.1
+1.0
6.4
%
%
%/°C
%/°C
k
%/°C
VOUT 0.3V to VDD 0.3V
VOUT 0.3V to VDD 0.3V
TA = -40 to +85°C
TA = -40 to +85°C
(Note 1)
(Note 1)
TA = -40 to +85°C
DC Output Non-linearity G = +1
VONL
— ±0.003
— % of FSR VOUT = 0.3V to VDD 0.3V, VDD = 5.0V
G +2
VONL
— ±0.001
— % of FSR VOUT = 0.3V to VDD 0.3V, VDD = 5.0V
Maximum Output Voltage Swing VOH, VOL VSS+20
VDD-100
mV G +2; 0.5V output overdrive
VSS+60
VDD-60
G +2; 0.5V output overdrive,
VREF = VDD/2
Short-Circuit Current
IO(SC)
±30
mA
Note 1: RLAD (RF + RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
DS21117A-page 2
2003 Microchip Technology Inc.

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MCP6S21/2/6/8
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, SI and SCK are tied low and CS is tied high.
Parameters
Sym Min Typ
Max Units
Conditions
Power Supply
Supply Voltage
VDD 2.5 —
5.5
V
Quiescent Current
IQ 0.5 1.0 1.35 mA IO = 0 (Note 2)
Quiescent Current, Shutdown
IQ_SHDN
0.5
1.0
µA IO = 0 (Note 2)
mode
Power-On Reset
POR Trip Voltage
VPOR
1.2
1.7
2.2
V (Note 3)
POR Trip Voltage Drift
VPOR/T
-3.0
— mV/°C TA = -40°C to+85°C
Note 1: RLAD (RF + RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, RL = 10 kto VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ
Max Units
Conditions
Frequency Response
-3 dB Bandwidth
BW
Gain Peaking
GPK
Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V THD+N
— 2 to 12
—0
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— 0.0015
MHz All gains; VOUT < 100 mVP-P (Note 1)
dB All gains; VOUT < 100 mVP-P
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 1 kHz, G = +4 V/V THD+N
0.0058
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 1 kHz, G = +16 V/V THD+N
0.023
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 20 kHz, G = +1 V/V THD+N
0.0035
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +4 V/V THD+N
0.0093
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +16 V/V THD+N
0.036
% VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
Step Response
Slew Rate
SR — 4.0 — V/µs G = 1, 2
— 11 — V/µs G = 4, 5, 8, 10
— 22 — V/µs G = 16, 32
Noise
Input Noise Voltage
Eni — 3.2 — µVP-P f = 0.1 Hz to 10 kHz (Note 2)
— 26 —
f = 0.1 Hz to 200 kHz (Note 2)
Input Noise Voltage Density
eni — 10 — nV/Hz f = 10 kHz (Note 2)
Input Noise Current Density
ini — 4 — fA/Hz f = 10 kHz
Note 1: See Table 4-1 for a list of typical numbers.
2: Eni and eni include ladder resistance noise. See Figure 2-33 for eni vs. G data.
2003 Microchip Technology Inc.
DS21117A-page 3

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MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min Typ Max Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
VIL 0 — 0.3VDD V
IIL
-1.0
+1.0
µA
VIH
0.7VDD
VDD
V
-1.0
+1.0
µA In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
Logic Threshold, High
SPI Timing
VOL
VOH
VSS
VDD-0.5
— VSS+0.4 V IOL = 2.1 mA, VDD = 5V
— VDD V IOH = -400 µA
Pin Capacitance
CPIN — 10 — pF All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
tRFI
2 µs Note 1
Output Rise/Fall Times (SO)
CS high time
tRFO
5 — ns MCP6S26 and MCP6S28
tCSH 40 — — ns
SCK edge to CS fall setup time
tCS0 10 — — ns SCK edge when CS is high
CS fall to first SCK edge setup time
tCSSC
40
— ns
SCK Frequency
SCK high time
SCK low time
SCK last edge to CS rise setup time
fSCK
tHI
tLO
tSCCS
40
40
30
— 10 MHz VDD = 5V (Note 2)
— — ns
— — ns
— — ns
CS rise to SCK edge setup time
tCS1
100 — —www.DataSheet4U.com
ns SCK edge when CS is high
SI set-up time
tSU 40 — — ns
SI hold time
tHD 10 — — ns
SCK to SO valid propagation delay
tDO
— — 80 ns MCP6S26 and MCP6S28
CS rise to SO forced to zero
tSOZ — — 80 ns MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
Gain Select Time
Shutdown Mode Timing
tCH — 1.5 — µs CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7VDD to VOUT 90% point
tG — 1 — µs CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7VDD to VOUT 90% point
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
tON — 3.5 10 µs CS = 0.7VDD to VOUT 90% point
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
tOFF
— 1.5 — µs CS = 0.7VDD to VOUT 90% point
POR Timing
Power-On Reset power-up time
tRPU — 30 — µs VDD = VPOR - 0.1V to VPOR + 0.1V,
50% VDD to 90% VOUT point
Power-On Reset power-down time tRPD — 10 — µs VDD = VPOR + 0.1V to VPOR - 0.1V,
50% VDD to 90% VOUT point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and
fall times of 5 ns. Maximum fSCK is, therefore, 5.8 MHz.
DS21117A-page 4
2003 Microchip Technology Inc.

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MCP6S21/2/6/8
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym Min Typ Max Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
TA
TA
TA
-40 — +85 °C
-40 — +125 °C (Note Note:)
-65 — +150 °C
Thermal Resistance, 8L-PDIP
θJA — 85 — °C/W
Thermal Resistance, 8L-SOIC
θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP
θJA
— 206 — °C/W
Thermal Resistance, 14L-PDIP
θJA
— 70 — °C/W
Thermal Resistance, 14L-SOIC
θJA
— 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA
— 100 — °C/W
Thermal Resistance, 16L-PDIP
θJA
— 70 — °C/W
Thermal Resistance, 16L-SOIC
θJA
— 90 — °C/W
Note 1: The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature
(150°C).
CS
tCH
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CS
tG
VOUT
FIGURE 1-1:
Diagram.
0.6V
0.3V
Channel Select Timing
VOUT
FIGURE 1-3:
Diagram.
1.5V
0.3V
Gain Select Timing
CS
tON
tOFF
VDD VPOR - 0.1V
VPOR + 0.1V
tRPU
VPOR - 0.1V
tRPD
VOUT
Hi-Z
0.3V
Hi-Z
ISS
500 nA (typ)
1.0 mA (typ)
FIGURE 1-2:
PGA Shutdown timing
diagram (must enter correct commands before
CS goes high).
VOUT
ISS
Hi-Z
500 nA (typ)
0.3V
1.0 mA (typ)
Hi-Z
FIGURE 1-4:
POR power-up and power-
down timing diagram.
2003 Microchip Technology Inc.
DS21117A-page 5