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32-Kb SPI Serial CMOS EEPROM
CAT25320
FEATURES
DESCRIPTION
„ 10 MHz SPI compatible
„ 1.8V to 5.5V supply voltage range
„ SPI modes (0,0) & (1,1)
„ 32-byte page write buffer
„ Self-timed write cycle
„ Hardware and software protection
„ Block write protection
– Protect 1/4, 1/2 or entire EEPROM array
„ Low power CMOS technology
„ 1,000,000 program/erase cycles
„ 100 year data retention
„ Industrial temperature range
„ RoHS-compliant 8 lead PDIP, SOIC, TSSOP and
8-pad TDFN packages
The CAT25320 is a 32-Kb Serial CMOS EEPROM
device internally organized as 4096x8 bits. This
features a 32-byte page write buffer and supports the
Serial Peripheral Interface (SPI) protocol. The device
is enabled through a Chip Select (C¯¯S) input. In
addition, the required bus signals are clock input
(SCK), data input (SI) and data output (SO) lines. The
H¯¯O¯L¯D¯ input may be used to pause any serial
communication with the CAT25320 device. The
device features software and hardware write protec–
tion, including partial as well as full array protection.
www.DataSheet4U.com
PIN CONFIGURATION
PDIP (L)
SOIC (V)
TSSOP (Y)
TDFN (VP2)
C¯¯S 1
SO 2
8 VCC
7 H¯¯O¯L¯D¯
¯W¯P¯ 3
6 SCK
VSS 4
5 SI
PIN FUNCTION
Pin Name
C¯¯S
SO
¯W¯P¯
VSS
SI
SCK
H¯¯O¯L¯D¯
VCC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
FUNCTIONAL SYMBOL
VCC
SI
CS
WP
HOLD
SCK
CAT25320
VSS
SO
For Ordering Information details, see page 15.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1111 Rev. E

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CAT25320
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND(4)
TDR
Parameter
Endurance
Data Retention
Ratings
–65 to +150
–0.5 to VCC + 0.5
Units
ºC
V
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, TA=-40°C to +85°C unless otherwise specified.
Symbol Parameter
ICC Supply Current
ISB1 Standby Current
ISB2 Standby Current
IL
ILO
VIL
VIH
VOL1
VOH1
VOL2
VOH2
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
Read, Write, VCC = 5.0V, fSCK = 10MHz,
SO open
VIN = GND or VCC , C¯¯S = VCC , ¯W¯P¯ = VCC,
VCC = 5.0V
VIN = GND or VCC , C¯¯S = VCC , ¯W¯P¯ = GND,
VCC = 5.0V
VIN = GND or VCC
C¯¯S = VCC , VOUT = GND or VCC
VCC 2.5V, IOL = 3.0mA
VCC 2.5V, IOH = -1.6mA
VCC < 2.5V, IOL = 150µA
VCC < 2.5V, IOH = -100µA
Min Max Units
2 mA
2 µA
4 µA
-2
-1
-0.5
0.7VCC
VCC - 0.8V
VCC - 0.2V
2
1
0.3VCC
VCC + 0.5
0.4
0.2
µA
µA
V
V
V
V
V
V
PIN CAPACITANCE(3)
TA = 25˚C, f = 1.0MHz, VCC = +5.0V
Symbol
COUT
CIN
Test
Output Capacitance (SO)
Input Capacitance (C¯¯S, SCK, SI, ¯W¯P¯, H¯¯O¯L¯D¯)
Conditions
VOUT = 0V
VIN = 0V
Min Typ
Max
8
8
Units
pF
pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. 1111 Rev. E
2 © 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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CAT25320
A.C. CHARACTERISTICS
TA = -40°C to +85°C, unless otherwise specified.(1)
Symbol
fSCK
tSU
tH
tWH
tWL
tLZ
tRI(2)
tFI(2)
tHD
tCD
tV
tHO
tDIS
tHZ
tCS
tCSS
tCSH
tWPS
tWPH
tWC(4)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
H¯¯O¯L¯D¯ to Output Low Z
Input Rise Time
Input Fall Time
H¯¯O¯L¯D¯ Setup Time
H¯¯O¯L¯D¯ Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
H¯¯O¯L¯D¯ to Output High Z
C¯¯S High Time
C¯¯S Setup Time
C¯¯S Hold Time
¯W¯P¯ Setup Time
¯W¯P¯ Hold Time
Write Cycle Time
Power-Up Timing(2)(3)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
VCC = 1.8V-5.5V
Min.
Max.
DC 5
30
30
75
75
50
2
2
0
10
75
0
50
100
50
50
50
10
10
5
VCC = 2.5V-5.5V
Min.
Max.
DC 10
20
20
40
40
25
2
2
0
10
40
0
20
25
15
15
15
10
10
5
Units
MHz
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Max.
1
1
Units
ms
ms
Notes:
(1) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: 10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(4) tWC is the time from the rising edge of C¯¯S after a valid write sequence to the end of the internal write cycle.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1111 Rev. E

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CAT25320
PIN DESCRIPTION
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25320.
C¯¯S: The chip select input pin is used to
enable/disable the CAT25320. When C¯¯S is high, the
SO output is tri-stated (high impedance) and the
device is in Standby Mode (unless an internal write
operation is in progress). Every communication
session between host and CAT25320 must be
preceded by a high to low transition and concluded
with a low to high transition of the C¯¯S input.
¯W¯P¯: The write protect input pin will allow all write
operations to the device when held high. When ¯W¯P¯
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
H¯¯O¯L¯D¯: The H¯¯O¯L¯D¯ input pin is used to pause trans–
mission between host and CAT25320, without
having to retransmit the entire sequence at a later
time. To pause, H¯¯O¯L¯D¯ must be taken low and to
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
pausing, the ¯H¯O¯L¯D¯ input should be tied to VCC,
either directly or through a resistor.
FUNCTIONAL DESCRIPTION
The CAT25320 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT25320 is accomplished
by simply providing the READ command and an
address. Writing to the CAT25320, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
After a high to low transition on the C¯¯S input pin, the
CAT25320 will accept any one of the six instruction op-
codes listed in Table 1 and will ignore all other possible
8-bit combinations. The communication protocol follows
the timing from Figure 1.
Table 1: Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Figure 1. Synchronous Data Timing
VIH
CS
VIL
SCK
SI
VIH
VIL
VIH
VIL
tCSS
tWH
tSU tH
VALID IN
SO VOH
VOL
HI-Z
Note: Dashed Line = mode (1, 1) - - - - - -
tCS
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
Doc. No. 1111 Rev. E
4 © 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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CAT25320
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The ¯R¯D¯Y¯ (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
The WPEN (Write Protect Enable) bit acts as an
enable for the ¯W¯P¯ pin. Hardware write protection is
enabled when the ¯W¯P¯ pin is low and the WPEN bit
is 1. This condition prevents writing to the status
register and to the block protected sections of
memory. While hardware write protection is active,
only the non-block protected memory can be written.
Hardware write protection is disabled when the ¯W¯P¯
pin is high or the WPEN bit is 0. The WPEN bit, ¯W¯P¯
pin and WEL bit combine to either permit or inhibit
Write operations, as detailed in Table 4.
Table 2. Status Register
76
WPEN
0
5
0
4 3 2 10
0
BP1
BP0
WEL
¯R¯D¯Y¯
Table 3. Block Protection Bits
Status Register Bits
BP1
BP0
00
01
10
11
Array Address Protected
None
0C00-0FFF
0800-0FFF
0000-0FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 4. Write Protect Conditions
WPEN
0
0
1
1
X
X
¯W¯P¯
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc. No. 1111 Rev. E