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CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
s 10 MHz SPI compatible
s 1,000,000 program/erase cycles
s 1.8 to 6.0 volt operation
s 100 year data retention
s Hardware and software protection
s Low power CMOS technology
s SPI modes (0,0 & 1,1)*
s Commercial, industrial, automotive and extended
rtstemperature ranges
s Self-timed write cycle
s 8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP
s 16/32-byte page write buffer
s Write protection
– Protect first page, last page, any 1/4 array or
lower 1/2 array
DESCRIPTION
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit
aSPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
Padvanced CMOS Technology substantially reduces
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
features a 32-byte page write buffer.The device operates
dvia the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C11/03/05/09/17 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
ePIN CONFIGURATION
www.DataSheet4U.com
uMSOP Package (R, Z, GZ)* SOIC Package (S, V, GV) DIP Package (P, L, GL) TSSOP Package (U, Y, GY)
CS 1
SO 2
tinWP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*CAT25C11/03 only
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
nPIN FUNCTIONS
oPin Name
Function
cSO
SCK
Serial Data Output
Serial Clock
isWP Write Protect
VCC +1.8V to +6.0V Power Supply
DVSS Ground
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SO
SI
CS
WP
HOLD
I/O
CONTROL
SPI
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
SCK
CS Chip Select
BLOCK
SI Serial Data Input
PROTECT
LOGIC
HOLD
NC
Suspends Serial Input
No Connect
DATA IN
STORAGE
* Other SPI modes available on request.
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1017, Rev. L

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CAT25C11/03/05/09/17
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. 55°C to +125°C Stresses above those listed under Absolute Maximum
Storage Temperature ....................... 65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) .................. 2.0V to +VCC +2.0V
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
VCC with Respect to VSS ................................ 2.0V to +7.0V
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation
mance and reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
rtsRELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(3)
TDR(3)
aVZAP(3)
PILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
dVCC = +1.8V to +6.0V, unless otherwise specified.
eSymbol
ICC1
uICC2
tinISB(6)
ILI
nILO
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Min.
Limits
Typ.
Max.
5
3
1
2
3
oVIL(5)
cVIH(5)
VOL1
isVOH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.7
VCC - 0.8
VCC x 0.3
VCC + 0.5
0.4
DVOL2
Output Low Voltage
0.2
Units
mA
mA
µA
µA
µA
V
V
V
V
V
Test Conditions
VCC = 5V @ 5MHz
SO=open; CS=Vss
VCC = 5.5V
FCLK = 5MHz
CS = VCC
VIN = VSS or VCC
VOUT = 0V to VCC,
CS = 0V
2.7VVCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
1.8VVCC<2.7V
VOH2
Output High Voltage
VCC-0.2
V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) VILMIN and VIHMAX are reference values only and are not tested.
(6) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1017, Rev. L
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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CAT25C11/03/05/09/17
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units Conditions
COUT Output Capacitance (SO)
8 pF VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF VIN=0V
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V 2.5V-6.0V
Min. Max. Min. Max.
4.5V-5.5V
Min. Max.
rtstSU Data Setup Time
50 20
20
tH Data Hold Time
50 20
20
tWH SCK High Time
250 75
40
atWL SCK Low Time
250 75
40
fSCK
PtLZ
tRI(1)
dtFI(1)
etHD
tCD
utWC(3)
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
DC 1 DC 5 DC 10
50 50 50
222
222
100 40
40
100 40
40
10 5
5
tintV Output Valid from Clock Low
250
75
40
tHO Output Hold Time
00
0
tDIS
tHZ
ntCS
otCSS
tCSH
ctWPS
istCSH
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
WP Setup Time
CS Hold Time
250
150
500 100
500 100
500 100
150 50
150 50
75
50
100
100
100
50
50
75
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
DInput Pulse Voltages: 0.3VCC to 0.7VCC
Test
UNITS Conditions
ns VIH = 2.4V
ns CL = 100pF
ns VOL = 0.8V
ns VOH = 2.0v
MHz
ns
µs CL = 50pF
µs (note 2)
ns
ns CL = 100pF
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input rise and fall times: 10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
(3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1017, Rev. L

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CAT25C11/03/05/09/17
FUNCTIONAL DESCRIPTION
the operation to be performed.
The CAT25C11/03/05/09/17 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to
interface directly with many of todays popular
microcontrollers. The CAT25C11/03/05/09/17 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C11/03/05/09/17.Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the 25C11/03/05/09/17. During a read cycle,
data is shifted out on the falling edge of the serial clock for
rtsFigure 1. Sychronous Data Timing
CS
aSO
1
2
NC
3
PNC
4
dNC
5
eNC
6
WP
7
uVSS
8
tinNote: Dashed Line= mode (1, 1) – – – –
16
15
14
13
12
11
10
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
INSTRUCTION SET
Instruction
nWREN
oWRDI
RDSR
cWRSR
isREAD
DWRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011(1)
0000 X010(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Power-Up Timing(2)(3)
Symbol
Parameter
Max.
Units
tPUR Power-up to Read Operation
1
tPUW
Power-up to Write Operation
1
Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
ms
ms
Doc. No. 1017, Rev. L
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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CAT25C11/03/05/09/17
SPI modes (0,0 & 1,1).
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
SCK: Serial Clock
05/09/17 draws ZERO current in the Standby mode. A
SCK is the serial clock pin. This pin is used to synchronize high to low transition on CS is required prior to any
the communication between the microcontroller and the sequence being initiated. A low to high transition on CS
25C11/03/05/09/17. Opcodes, byte addresses, or data after a valid write sequence is what initiates an internal
present on the SI pin are latched on the rising edge of the write cycle.
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C11/
03/05/09/17 and CS high disables the CAT25C11/03/05/
09/17. CS high takes the SO output pin to high impedance
rtsBYTE ADDRESS
normal read/write operations when held high. When WP is
tied low and the WPEN bit in the status register is set to "1",
all write operations to the status register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated, WP going low will have no effect on any write
Device
Address Significant Bits
Address Don't Care Bits # Address Clock Pulse
CAT25C11
A6 - A0
A7 8
aCAT25C03
A7 - A0
8
CAT25C05 A7 - A0 (A8 = X bit from Opcode)
8
PCAT25C09
A9 - A0
A15 - A10
16
CAT25C17
A10 - A0
A15 - A11
16
dSTATUS REGISTER
7
eWPEN
6
1
543210
1
BP2
BP1
BP0
WEL
RDY
uMEMORY PROTECTION
tinBP2 BP1 BP0
0 0 0 Non-Protection
0 0 1 Q1 Protected
0 1 0 Q2 Protected
n0 1 1 Q3 Protected
o1 0 0 Q4 Protected
1 0 1 H1 Protected
c1 1 0 P0 Protected
is1 1 1 Pn Protected
WRITE PROTECT ENABLE OPERATION
25C11 25C03 25C05 25C09 25C17
Q1 00-1F 00-3F 000-07F 000-0FF 000-1FF
Q2 20-3F 40-7F 080-0FF 100-1FF 200-3FF
Q3 40-5F 80-BF 100-17F 200-2FF 400-5FF
Q4 60-7F C0-FF 180-1FF 300-3FF 600-7FF
H1 00-3F 00-7F 000-0FF 000-1FF 000-3FF
P0 00-0F 00-0F 000-00F 000-01F 000-01F
Pn 70-7F F0-FF 1F0-1FF 3E0-3FF 7E0-7FF
D Protected
Unprotected
Status
WPEN WP WEL
Blocks
Blocks
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1
Low 0
Protected
Protected
Protected
1
Low 1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1017, Rev. L