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80C154/83C154
CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller
Description
TEMIC’s 80C154 and 83C154 are high performance
CMOS single chip µC. The 83C154 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 I/O lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features : 32 bit timer and watchdog functions. Timer 0
and 1 can be configured by program to implement a 32 bit
timer. The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C154 has 2 software-selectable modes
of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C154 is identical to the 83C154 except that it has
no on-chip ROM. TEMIC’s 80C154 and 83C154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vcc = 5 V.
D 80C154 : ROMless version of the 83C154µ
D 80C154/83C154-12 : 0 to 12 MHz
D 80C154/83C154-16 : 0 to 16 MHz
D 80C154/83C154-20 : 0 to 20 MHz
D 80C154/83C154-25 : 0 to 25 MHz
D 80C154/83C154-30 : 0 to 30 MHz
D 80C154/83C154-36 : 0 to 36 MHz
D 80C154/83C154-L16 : Low power version
VCC : 2.7-5.5 V Freq : 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
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D Power control modes
D 256 bytes of RAM
D 16 Kbytes of ROM (83C154)
D 32 Programmable I/O lines (programmable impedance)
D Three 16 bit timer/counters (including watchdog and 32 bit
timer)
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
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Rev.F (14 Jan. 97)
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80C154/83C154
Interface
Figure 1. Block Diagram
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Rev.F (14 Jan. 97)

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Figure 2. Pin Configuration
80C154/83C154
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
80C154/83C154
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
NC
ALE
PSEN
P2.7/A14
P2.6/A13
P2.5/A12
DIL
P15
P16
P17
RST
RxD/P30
NC
TxD/P31
INT0/P32
INT1/P33
T0/P34
T1/P35
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80C154/83C154
LCC
P04 /A4
P05 /A5
P06 /A6
P07 /A7
EA
NC
ALE
PSEN
P27 /A15
P26 /A14
P25 /A13
Flat Pack
Diagrams are for reference only. Package sizes are not to scale
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80C154/83C154
Pin Description
Vss Port 2
Circuit Ground Potential.
Port 2 is an 8 bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1’s written to them are
VCC
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
Supply voltage during normal, Idle, and Power Down being pulled low will source current (ILL, on the data
operation.
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Port 0
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOVX @DPTR). In
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have 1’s written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1’s. Port 0 also outputs the code bytes
during program verification in the 83C154. External
this application, it uses strong internal pullups when
emitting 1’s. During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C154. Port
2 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
pullups are required during program verification. Port 0 Port 3
can sink eight LS TTL inputs.
Port 3 is an 8 bit bi-directional I/O port with internal
Port 1
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
Port 1 is an 8 bit bi-directional I/O port with internal be used as inputs. As inputs, Port 3 pins that are externally
pullups. Port 1 pins that have 1’s written to them are being pulled low will source current (ILL, on the data
pulled high by the internal pullups, and in that state canwww.DastahSeheeett4)U.bcoemcause of the pullups. It also serves the functions
be used as inputs. As inputs, Port 1 pins that are externally of various special features of the TEMIC 51 Family, as
being pulled low will source current (IIL, on the data listed below.
sheet) because of the internal pullups.
Port Pin
Alternate Function
Port 1 also receives the low-order address byte during
program verification. In the 83C154, Port 1 can sink or
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
2 inputs of PORT 1 are also used for timer/counter 2 :
P1.0 [T2] : External clock input for timer/counter 2. P1.1
[T2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 TD (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
P3.6 WR (external Data Memory write strobe)
P3.7 RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to VCC. As soon as the result is
applied (Vin), PORT 1, 2 and 3 are tied to 1. This
operation is achieved asynchronously even if the
oscillator is not start up.
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80C154/83C154
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
PSEN
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
EA
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds
3FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
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Idle and Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INT0, INT1, T0, T1).
Figure 3. Idle and Power Down Hardware.
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
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