AT87C51RB2.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AT87C51RB2 데이타시트 다운로드

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1. Features
80C52 Compatible
– 8051 pin and instruction compatible
– Four 8-bit I/O ports
– Three 16-bit timer/counters
– 256 bytes scratchpad RAM
High-Speed Architecture
– 40 MHz @ 5V, 30MHz @ 3V
– X2 Speed Improvement capability (6 clocks/machine cycle)
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
– 60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Programmable Counter Array with
– High Speed Output,
– Compare / Capture,
– Pulse Width Modulator,
– Watchdog Timer Capabilities
Hardware Watchdog Timer (One-time enabled with Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high pin count packages
Asynchronous port reset
Interrupt Structure with
– 7 Interrupt sources,
– 4 level priority interrupt system
Full duplex Enhanced UART
– Framing error detection
– Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
– Idle mode
– Power-down mode
– Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4
2. Description
Atmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit microcontroller.
The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM
capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or
768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that
High
Performance
8-bit
Microcontroller
TS80C51RA2
TS83C51RB2
TS83C51RC2
TS83C51RD2
TS87C51RB2
TS87C51RC2
TS87C51RD2
AT80C51RA2
AT83C51RB2
AT83C51RC2
AT83C51RD2
AT87C51RB2
AT87C51RC2
Rev. 4188F–8051–01/08

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facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to reduce system power consumption by
bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in
power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the
interrupt system are still operating. In the power-down mode the RAM is saved and all other
functions are inoperative.
PDIL40
PLCC44
VQFP44 1.4
TS80C51RA2
TS80C51RD2
TS83C51RB2
TS83C51RC2
TS83C51RD2
TS87C51RB2
TS87C51RC2
TS87C51RD2
ROM (bytes)
0
0
16k
32k
64k
0
0
0
EPROM (bytes)
0
0
0
0
0
16k
32k
64k
XRAM (bytes)
256
768
256
256
768
256
256
768
TOTAL RAM
(bytes)
512
1024
512
512
1024
512
512
1024
I/O
32
32
32
32
32
32
32
32
PLCC68
VQFP64 1.4
TS80C51RD2
TS83C51RD2
TS87C51RD2
ROM (bytes)
0
64k
0
EPROM (bytes)
0
0
64k
XRAM (bytes)
768
768
768
TOTAL RAM
(bytes)
1024
1024
1024
I/O
48
48
48
2 AT/TS8xC51Rx2
4188F–8051–01/08

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3. Block Diagram
AT/TS8xC51Rx2
XTAL1
XTAL2
ALE/PROG
PSEN
EA/VPP
RD
WR
(3)
(3)
(3) (3)
(1) (1) (1) (1)
EUART
RAM
256x8
ROM
/EPROM
XRAM
0/16/32/64Kx8 256/768x8
PCA
Timer2
CPU
C51
CORE
IB-bus
Timer 0
Timer 1
INT
Ctrl
(3) (3) (3) (3)
Parallel I/O Ports & Ext. Bus
Port
0
Port
1
Port
2
Port
3
Port
(2)
4
Port
(2)
5
Watch
Dog
(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3
4188F–8051–01/08
3

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4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3, P4, P5
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
4 AT/TS8xC51Rx2
4188F–8051–01/08

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AT/TS8xC51Rx2
Bit
addressable
0/8
F8h
F0h
B
0000 0000
P5 bit
E8h addressable
1111 1111
E0h
ACC
0000 0000
D8h
CCON
00X0 0000
D0h
PSW
0000 0000
C8h
T2CON
0000 0000
P4 bit
C0h addressable
1111 1111
B8h
IP
X000 000
B0h
P3
1111 1111
A8h
IE
0000 0000
A0h
P2
1111 1111
98h
SCON
0000 0000
90h
P1
1111 1111
88h
TCON
0000 0000
80h
P0
1111 1111
0/8
reserved
Table 4-1. All SFRs with their address and their reset value
Non Bit addressable
1/9
CH
0000 0000
2/A
CCAP0H
XXXX XXXX
3/B
CCAP1H
XXXX XXXX
4/C
CCAPL2H
XXXX XXXX
5/D
CCAPL3H
XXXX XXXX
6/E
CCAPL4H
XXXX XXXX
CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPL2L
XXXX XXXX
CCAPL3L
XXXX XXXX
CCAPL4L
XXXX XXXX
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
SADEN
0000 0000
SADDR
0000 0000
SBUF
XXXX XXXX
AUXR1
XXXX0XX0
WDTRST
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
TH0
0000 0000
4/C
TH1
0000 0000
5/D
AUXR
XXXXXX00
6/E
7/F
P5 byte
addressable
1111 1111
IPH
X000 0000
WDTPRG
XXXX X000
CKCON
XXXX XXX0
PCON
00X1 0000
7/F
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
4188F–8051–01/08
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