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Data Sheet
Broadband Modem Mixed-Signal Front End
AD9866
FEATURES
Low cost 3.3 V CMOS MxFE for broadband modems
12-bit DAC
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 23 dBm line driver with 19.5 dB gain control
12-bit, 80 MSPS ADC
−12 dB to +48 dB low noise RxPGA (<2.5 nV/√Hz)
Third order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Backward-compatible with AD9975 and AD9876
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in 64-lead chip scale package or bare die
APPLICATIONS
Powerline networking
VDSL and HPNA
FUNCTIONAL BLOCK DIAGRAM
PWR DWN
MODE
TXEN/SYNC
TXCLK
ADIO[11:6]/
Tx[5:0]
ADIO[5:0]/
Rx[5:0]
RXE/SYNC
RXCLK
AGC[5:0]
SPI
AD9866
12
2-4X
TxDAC
IAMP
0 TO –7.5dB
0 TO –12dB
CLK
SYN.
2M CLK
MULTIPLIER
12
ADC
80MSPS
2-POLE
LPF
1-POLE
LPF
6
4 REGISTER
CONTROL
0 TO 6dB – 6 TO 18dB –6 TO 24dB
= 1dB = 6dB
= 6dB
IOUT_G+
IOUT_N+
IOUT_N–
IOUT_G–
CLKOUT_1
CLKOUT_2
OSCIN
XTAL
RX+
RX–
Figure 1.
GENERAL DESCRIPTION
The AD9866 is a mixed-signal front end (MxFE®) IC for
transceiver applications requiring Tx and Rx path functionality
with data rates up to 80 MSPS. Its flexible digital interface, power
saving modes, and high Tx-to-Rx isolation make it well-suited
for half- and full-duplex applications. The digital interface is
extremely flexible allowing simple interfaces to digital back
ends that support half- or full-duplex data transfers, thus often
allowing the AD9866 to replace discrete ADC and DAC
solutions. Power saving modes include the ability to reduce
power consumption of individual functional blocks or to power
down unused blocks in half-duplex applications. A serial port
interface (SPI®) allows software programming of the various
functional blocks. An on-chip PLL clock multiplier and
synthesizer provide all the required internal clocks, as well as
two external clocks from a single crystal or clock source.
The Tx signal path consists of a bypassable 2×/4× low-pass
interpolation filter, a 12-bit TxDAC, and a line driver. The
transmit path signal bandwidth can be as high as 34 MHz at an
input data rate of 80 MSPS. The TxDAC provides differential
current outputs that can be steered directly to an external load
or to an internal low distortion current amplifier. The current
amplifier (IAMP) can be configured as a current- or voltage-
mode line driver (with two external npn transistors) capable of
delivering in excess of 23 dBm peak signal power. Tx power can
be digitally controlled over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier
(RxPGA), a tunable low pass filter (LPF), and a 12-bit ADC.
The low noise RxPGA has a programmable gain range of
−12 dB to +48 dB in 1 dB steps. Its input referred noise is less
than 3.3 nV/√Hz for gain settings beyond 30 dB. The receive
path LPF cutoff frequency can be set over a 15 MHz to 35 MHz
range or simply bypassed. The 12-bit ADC achieves excellent
dynamic performance over a 5 MSPS to 80 MSPS span. Both
the RxPGA and the ADC offer scalable power consumption
allowing power/performance optimization.
The AD9866 provides a highly integrated solution for many
broadband modems. It is available in a space saving, 64-lead
lead frame chip scale package (LFCSP), and is specified over the
commercial (−40°C to +85°C) temperature range.
Rev. C
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Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9866* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Application Notes
• AN-700: Instructions for the AD9865/AD9866 Evaluation
Software
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
Data Sheet
• AD9866: Broadband Modem Mixed-Signal Front End Data
Sheet
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Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
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AD9866
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Tx Path Specifications.................................................................. 3
Rx Path Specifications.................................................................. 4
Power Supply Specifications........................................................ 5
Digital Specifications ................................................................... 6
Serial Port Timing Specifications ............................................... 7
Half-Duplex Data Interface (ADIO Port) Timing
Specifications ................................................................................ 7
Full-Duplex Data Interface (Tx and Rx PORT) Timing
Specifications ................................................................................ 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Rx Path Typical Performance Characteristics ........................ 12
TxDAC Path Typical Performance Characteristics ............... 16
IAMP Path Typical Performance Characteristics .................. 18
Serial Port ........................................................................................ 19
Register Map Description.......................................................... 21
Serial Port Interface (SPI).......................................................... 21
Digital Interface .............................................................................. 23
Half-Duplex Mode ..................................................................... 23
Full-Duplex Mode ...................................................................... 24
RxPGA Control .......................................................................... 26
TxPGA Control .......................................................................... 27
REVISION HISTORY
8/2016—Rev. B to Rev. C
Changed Thermal Characteristics Section to Thermal Resistance
Section ........................................................................................................... 10
Changes to Thermal Resistance Section...............................................10
Added Table 9; Renumbered Sequentially ...........................................10
8/2011—Rev. A to Rev. B
Deleted Lead Temperature Range Parameter, Table 8......................... 9
Moved Explanation of Test Levels............................................................ 9
Added EPAD Note to Figure 2 and Added EPAD Note
to Table 9.......................................................................................................10
Changes to Figure 53 .................................................................................24
Changes to Figure 54 .................................................................................25
Transmit Path.................................................................................. 28
Digital Interpolation Filters ...................................................... 28
TxDAC and IAMP Architecture .............................................. 29
Tx Programmable Gain Control .............................................. 30
TxDAC Output Operation........................................................ 30
IAMP Current-Mode Operation.............................................. 30
IAMP Voltage-Mode Operation............................................... 31
IAMP Current Consumption Considerations........................ 32
Receive Path .................................................................................... 33
Rx Programmable Gain Amplifier........................................... 33
Low-Pass Filter............................................................................ 33
Analog-to-Digital Converter (ADC)....................................... 35
AGC Timing Considerations.................................................... 36
Clock Synthesizer ........................................................................... 37
Power Control and Dissipation .................................................... 39
Power-Down ............................................................................... 39
Half-Duplex Power Savings ...................................................... 39
Power Reduction Options ......................................................... 40
Power Dissipation....................................................................... 42
Mode Select upon Power-Up and Reset.................................. 42
Analog and Digital Loopback Test Modes.............................. 43
PCB Design Considerations.......................................................... 44
Component Placement .............................................................. 44
Power Planes and Decoupling .................................................. 44
Ground Planes ............................................................................ 44
Signal Routing............................................................................. 45
Evaluation Board ............................................................................ 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
Changes to Figure 59................................................................................. 28
12/2004—Rev. 0 to Rev. A
Changes to Specifications Tables...............................................................3
Changes to Serial Table............................................................................. 19
Changes to Full Duplex Mode section.................................................. 24
Changes to Table 14................................................................................... 25
Change to TxDAC and IAMP Architecture section ......................... 29
Change to TxDAC Output Operation section.................................... 30
Insert equation............................................................................................ 37
Change to Figure 84 caption ................................................................... 42
11/2003—Revision 0: Initial Version
Rev. C | Page 2 of 47

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Data Sheet
AD9866
SPECIFICATIONS
Tx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 kΩ, unless otherwise noted.
Table 1.
Parameter
TxDAC DC CHARACTERISTICS
Resolution
Update Rate
Full-Scale Output Current (IOUTP_FS)
Gain Error1
Offset Error
Voltage Compliance Range
TxDAC GAIN CONTROL CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
TxDAC AC CHARACTERISTICS2
Fundamental
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
IAMP DC CHARACTERISTICS
IOUTN Full-Scale Current = IOUTN+ + IOUTN−
IOUTG Full-Scale Current = IOUTG+ + IOUTG−
AC Voltage Compliance Range
IAMPN AC CHARACTERISTICS3
Fundamental
IOUTN SFDR (Third Harmonic)
IAMP GAIN CONTROL CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
IOUTN Gain Range Error
REFERENCE
Internal Reference Voltage4
Reference Error
Reference Drift
Tx DIGITAL FILTER CHARACTERISTICS (2× INTERPOLATION)
Latency (Relative to 1/fDAC)
−0.2 dB Bandwidth
−3 dB Bandwidth
Stop-Band Rejection (0.289 fDAC to 0.711 fDAC)
Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)
Latency (Relative to 1/fDAC)
−0.2 dB Bandwidth
−3 dB Bandwidth
Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN)
Temp Test Level Min
Typ Max Unit
Full
Full II
Full IV
25°C I
25°C V
Full
12 Bits
200 MSPS
2 25 mA
±2 % FS
2 µA
−1 +1.5 V
25°C V
25°C V
25°C V
25°C IV
25°C V
−7.5
0
0.5
Monotonic
±2
dB
dB
dB
dB
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
25°C
Full IV
25°C V
25°C V
25°C V
25°C IV
25°C V
25°C I
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
0.5 dBm
66.6 69.2
dBc
68.4 69.8
dBc
−79 −68.7 dBc
68.5 81
dBc
2 105 mA
2 150 mA
1 7V
13
43.3 45.2
dBm
dBc
−19.5
0
0.5
Monotonic
0.5
dB
dB
dB
dB
dB
1.23
0.7 3.4
30
V
%
ppm/oC
43
0.2187
0.2405
50
Cycles
fOUT/fDAC
fOUT/fDAC
dB
96
0.1095
0.1202
50
Cycles
fOUT/fDAC
fOUT/fDAC
dB
Rev. C | Page 3 of 47

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AD9866
Data Sheet
Parameter
PLL CLK MULTIPLIER
OSCIN Frequency Range
Internal VCO Frequency Range
Duty Cycle
OSCIN Impedance
CLKOUT1 Jitter5
CLKOUT2 Jitter6
CLKOUT1 and CLKOUT2 Duty Cycle7
Temp Test Level Min
Full IV
Full IV
Full II
25°C V
25°C III
25°C III
Full III
5
20
40
45
Typ Max Unit
100//3
12
6
80
200
60
55
MHz
MHz
%
ΜΩ//pF
ps rms
ps rms
%
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4× interpolation.
3 IOUN full-scale current = 80 mA, fOSCIN= 80 MHz, fDAC=160 MHz, 2× interpolation.
4 Use external amplifier to drive additional load.
5 Internal VCO operates at 200 MHz , set to divide-by-1.
6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.
7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias
settings, unless otherwise noted.
Table 2.
Parameter
Rx INPUT CHARACTERISTICS
Input Voltage Span (RxPGA gain = −10 dB)
Input Voltage Span (RxPGA gain = +48 dB)
Input Common-Mode Voltage
Differential Input Impedance
Temp Test Level
Full III
Full III
25°C III
25°C III
Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)
Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz)
Input Voltage Noise Density (RxPGA Gain = 48 dB, f−3 dBF = 26 MHz)
RxPGA CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
RxLPF CHARACTERISTICS
Cutoff Frequency (f−3 dBF ) range
Attenuation at 55.2 MHz with f−3 dBF = 21 MHz
Pass-Band Ripple
Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS
Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS
ADC DC CHARACTERISTICS
Resolution
Conversion Rate
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
NA
FULL
III
III
III
III
III
III
III
III
III
III
III
III
III
NA
II
Min Typ
Max Unit
6.33 V p-p
8 mV p-p
1.3 V
400 Ω
4.0 pF
53 MHz
2.7 nV/√Hz
2.4 nV/√Hz
−12
48
1
Monotonic
0.5
dB
dB
dB
dB
dB
15
20
±1
20
100
35 MHz
dB
dB
ns
ns
12
5
Bits
80 MSPS
Rev. C | Page 4 of 47