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SY58611U
3.2Gbps Precision, LVDS 2:1 MUX with
Internal Termination and Fail Safe Input
General Description
The SY58611U is a 2.5V, high-speed, fully differential
LVDS 2:1 MUX capable of processing clocks up to
2.5GHz and data up to 3.2Gbps. SY58611U is
optimized to provide a buffered output of the selected
input with less than 20ps of skew and less than 10pspp
total jitter. Patented MUX Isolation design reduces
crosstalk and provides superior signal integrity.
The differential inputs include Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mVPK (200mVpp) without any level-
shifting or termination resistor networks in the signal
path. For AC-coupled input interface applications, an
integrated reference voltage (VREF-AC) is provided to bias
the VT pin. The output is LVDS compatible, with rise/fall
times guaranteed to be less than 120ps.
The SY58611U operates from a 2.5V ±5% supply and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require CML or
LVPECL output, consider the SY58609U and
SY58610U, 2:1 MUX with 400mV and 800mV output
swings respectively. The SY58611U is part of Micrel’s
high-speed, Precision Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Features
Precision Edge®
Selects between two sources and provides buffered
copy of the selected input signal
Fail Safe Input
– Prevents output from oscillating when input is
invalid or removed
Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <420ps typical propagation delay (IN-to-Q)
– <120ps rise/fall times
Unique, patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
2.5V ±5% power supply operation
Industrial temperature range: –40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Applications
All SONET clock distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock or data distribution
Backplane distribution
Markets
DataCom and Telecom
Storage
ATE
Test and Measurement
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2007
M9999-030607-A
hbwhelp@micrel.com or (408) 955-1690

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Micrel, Inc.
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
SY58611UMG
SY58611UMGTR(2)
QFN-16
QFN-16
Industrial
Industrial
611U with Pb-Free
bar-line indicator
611U with Pb-Free
bar-line indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
Truth Table
SEL
0
1
Output
IN0 Selected
IN1 Selected
SY58611U
16-Pin QFN
Pin Description
Pin Number
1, 4
Pin Name
VT0, VT1
2, 3 VREF-AC0,
VREF-AC1
5, 6
15, 16
IN1, /IN1
IN0, /IN0
7 SEL
8, 13
9, 12
VCC
/Q, Q
10, 11
14
GND,
Exposed pad
NC
Pin Function
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” subsection.
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its
respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signals as small as 100mV (200mVPP). Each pin of the
pairs internally terminates with 50to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by
latching the output to its last valid state. See “Input Interface Applications” subsection.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kpull-up resistor and will default
to logic HIGH state if left open. The input-switching threshold is VCC/2.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins
as possible.
LVDS Differential Output Pair: Differential buffered output copy of the selected input signal. The
output swing is typically 325mV. Normally terminated 100_ across the output (Q and /Q). See
“LVDS Output Interface Applications” subsection.
Ground. Exposed pad must be connected to a ground plane that is the same potential as the
ground pin.
No connect.
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. –0.5V to +4.0V
Input Voltage (VIN) ......................................... –0.5V to VCC
LVDS Output Current (IOUT) ................................... ±10mA
Input Current
Source or Sink Current on (IN, /IN)................. ±50mA
Current (VREF)
Source or
sink
current
on
VREF-AC(4)
...............
±0.5mA
Maximum operating Junction Temperature ............125°C
Lead Temperature (soldering, 20sec.) ....................260°C
Storage Temperature (Ts) ...................... –65°C to +150°C
SY58611U
Operating Ratings(2)
Supply Voltage (VCC) ....................... +2.375V to +2.635V
APmacbkiaegnet TTehmerpmeraal tRureesi(sTtaA)n.c..e..(.3.).............. –40°C to +85°C
QFN
Still-air (qJA) .............................................. 60°C/W
Junction-to-Board (yJB)........................... 33°C/W
DC Electrical Characteristics(5)
TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
VCC Power Supply Voltage Range
ICC Power Supply Current
No load, max. VCC
2.375
2.5 2.625 V
40 60 mA
RIN Input Resistance
(IN-to-VT, /IN-to-VT)
45 50 55
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
90
100 110
VIH Input HIGH Voltage
(IN, /IN)
1.2
VCC
V
VIL Input LOW Voltage
(IN, /IN)
0.2
VIH–0.1
V
VIN Input Voltage Swing
(IN, /IN)
see Figure 3a, Note 6
0.1 1.0 V
VDIFF_IN
Differential Input Voltage Swing see Figure 3b
(|IN - /IN|)
0.2
V
VIN_FSI
Input Voltage Threshold that
Triggers FSI
30 100 mV
VREF-AC
AC Reference Voltage
IVREF-AC = + 0.5mA
VCC-1.3
VCC-1.0
V
VT_IN
Voltage from Input to VT
1.28 V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. yJB and qJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. VIN (max) is specified when VT is floating.
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SY58611U
LVDS Output DC Electrical Characteristics(7)
VCC = +2.5V ±5%, RL = 100across the output pair; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ
VOUT
VDIFF_OUT
VOCM
DVOCM
Output Voltage Swing (Q, /Q)
Differential Output Voltage Swing |Q-/Q|
Output Common Mode Voltage (Q, /Q)
Change in Common Mode Voltage (Q, /Q)
See Figure 3a
See Figure 3b
See Figure 5b
See Figure 5b
250
500
1.125
–50
325
650
1.20
Max
1.275
50
Units
mV
mV
V
mV
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V ±5%; TA = –40°C to + 85°C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max
VIH Input HIGH Voltage
2.0
VIL Input LOW Voltage
0.8
IIH Input HIGH Current
-125
30
IIL Input LOW Current
-300
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Units
V
V
µA
µA
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SY58611U
AC Electrical Characteristics(8)
VCC = +2.5V ±5%, RL = 100across the output pair; Input tr/tf < 300ps, TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
fMAX Maximum Frequency
NRZ Data
VOUT > 200mV
tPD
Propagation Delay
IN-to-Q VIN: 100mV-200mV
VIN: > 200mV
SEL-to-Q
3.2 Gbps
Clock 2.5
3
GHz
190 330 470 ps
150 280 420 ps
150 450 ps
tSkew
Input-to-Input Skew
Part-to-Part Skew
Note 9, 10
Note 11
5 20 ps
150 ps
tJitter
Data
Random Jitter
Note 12
Deterministic Jitter Note 13
Clock
Cycle-to-Cycle Jitter Note 14
Total Jitter
Note 15
tr, tf Output Rise/Fall Times
(20% to 80%)
At full output swing.
1 psRMS
10 psPP
1 psRMS
10 psPP
40 80 120 ps
Duty Cycle
Differential I/O
47 53 %
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Input-to-Input skew is the time difference between the two inputs and one output, under identical input transitions.
10. Input-to-Input Skew is included in IN-to-Q propagation delay.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at
the edges at the respective inputs.
12. Random jitter is measured with a K28.7 pattern, measured at fMAX.
13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
March 2007
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hbwhelp@micrel.com or (408) 955-1690