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Semiconductor
NOT
RECOMMENSDeEe DHIF1O17R9NEW
DESIGNS
HI1176
October 1998
8-Bit, 20 MSPS, Flash A/D Converter
Features
Description
• Resolution ±0.5 LSB (DNL) . . . . . . . . . . . . . . . . . . . 8-Bit The HI1176 is an 8-bit, CMOS analog-to-digital converter for
[/MTaitxliem(uHmI1S1am76p)ling Frequency . . . . . . . . . . . 20 MSPS
video use that features a sync clamp function. The adoption
of a 2-step parallel method realizes low power consumption
/SLuobwjePcot w(8e-rBCiotn, s2u0mMptSioPnSa,t F20laMshSPAS/D(TyCp)onverter) and a maximum conversion speed of 20 MSPS. For higher
/A(Rutehfeorren()ce Current Excluded) . . . . . . . . . . . . . . .60mW sampling rates, refer to the pin-for-pin compatible HI1179
/KBeuyiwlt-oInrdSsyn(cHCalrarmispSFeumncictioonnductor, Video, Image Scadna-ta sheet, AnswerFAX document number 3666.
neBr,uPiltC-InVMidoenoosctaabplteuMreu,ltSiveitbtroatporbfooxr ,CClalmamp Ppu, lIsneternal RAepf-plications
erGenecnee)ration
/CBreuailtt-oInr (S)ync Pulse Polarity Selection Function
• Video Digitizing
/DOCINFO pdfmark
• Image Scanners
• Clamp Pulse Direct Input Possible
• Low Cost High Speed Data Acquisition Systems
[/BPuaiglte-IMn Coldaem/pUOsNe/OOuFFtliFnuensction
• Multimedia
/DBOuCiltV-InIERWeferpednfcme aVorkltage Self Bias Circuit
• Input CMOS Compatible
Ordering Information
• Three-State TTL Compatible Output
• Single +5V Power Supply
• Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . 11pF
www.DataSheet4U.com • Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 300
PART
NUMBER
HI1176JCQ
HI1176-EV
TEMP. RANGE
(oC)
PACKAGE PKG. NO.
-40 to 85
32 Ld MQFP Q32.7x7-S
25 Evaluation Board
• Direct Replacement for the Sony CXD1176
Pinout
HI1176
(MQFP)
TOP VIEW
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
VRB
AVSS
AVSS
VIN
AVDD
AVDD
VRT
VRTS
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
4-1
File Number 3582.5

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HI1176
Functional Block Diagram
OE 30
DVSS 31
28
DVSS
D0 (LSB) 1
D1 2
D2 3
LOWER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
D3 4
D4 5
D5 6
D6 7
D7 (MSB) 8
UPPER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
UPPER
ENCODER
(4-BIT)
DVDD 10
DVDD 11
CLK 12
CLOCK GENERATOR
NC 9
NC 32
REFERENCE SUPPLY
LOWER SAMPLING
COMPARATOR
(4-BIT)
LOWER SAMPLING
COMPARATOR
(4-BIT)
UPPER SAMPLING
COMPARATOR
(4-BIT)
-
+
29 27 26
CLE CCP VREF
M•M
25 VRBS
24 VRB
23 AVSS
22 AVSS
21 VIN
20 AVDD
19 AVDD
18 VRT
17 VRTS
16 AVDD
15 PW
14 SYNC
13 SEL
Typical Application Schematic
WHEN CLAMP IS NOT USED (SELF BIAS USED)
CLOCK IN
HCO4
+5V (DIGITAL)
0.1µF
VIDEO IN
+5V (ANALOG)
0.01µF
75
10pF
0.1µF
0.01µF
16 15 14 13 12 11 10 9
17 8
18 7
19 6
20 5
21 4
22 3
23 2
24 1
25 26 27 28 29 30 31 32
D7
D6
D5
D4
D3
D2
D1
D0
GND (ANALOG)
GND (DIGITAL)
+5V (DIGITAL)
4-2

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HI1176
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage, VRT, VRB . . . . . . . . . VDD + 0.5V to VSS - 0.5V
Analog Input Voltage, VIN. . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V
Digital Input Voltage, CLK. . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V
Digital Output Voltage, VOH, VOL . . . . . . . VDD + 0.5V to VSS - 0.5V
Operating Conditions (Note 1)
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(Lead Tips Only)
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage
AVDD, AVSS, DVDD, DVSS . . . . . . . . . . . . . . . +4.75V to +5.25V
|DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV
Reference Input Voltage
VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above
VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below
Analog Input Voltage, VIN. . . . . . . . . VRB to VRT (1.8VP-P to AVDD)
Clock Pulse Width
tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SYSTEM PERFORMANCE
Offset Voltage
EOT
EOB
Integral Non-Linearity, INL
Differential Non-Linearity, DNL
DYNAMIC CHARACTERISTICS
fC = 20 MSPS, VIN = 0.5V to 2.5V
fC = 20 MSPS, VIN = 0.5V to 2.5V
-60 -40 -20 mV
+20 +40 +60 mV
- ±0.5 ±1.3 LSB
- ±0.3 ±0.5 LSB
Signal to Noise Ratio, SINAD
S-----i-g---n----a---l----T---o-------N-----o---i-s---e-R----+M-----S-D----i-Ss---t-i-o-g--r-n--t-ia-o---l-n-----R----a---t--i-o---,----S----I--N----A----D---
fS = 20MHz, fIN = 1MHz
fS = 20MHz, fIN = 3.58MHz
Maximum Conversion Speed, fC
VIN = 0.5V to 2.5V, fIN = 1kHz Ramp
Minimum Conversion Speed
- 46 - dB
- 46 - dB
20 35
- MSPS
- - 0.5 MSPS
Differential Gain Error, DG
Differential Phase Error, DP
NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS
- 1.0 -
%
- 0.5 - Degree
Aperture Jitter, tAJ
Sampling Delay, tDS
ANALOG INPUTS
- 30 - ps
- 4 - ns
Analog Input Bandwidth (-1dB), BW
- 18 - MHz
Analog Input Capacitance, CIN
VIN = 1.5V + 0.07VRMS
- 11 - pF
4-3

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HI1176
Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
REFERENCE INPUT
Reference Pin Current, IREF
Reference Resistance (VRT to VRB), RREF
INTERNAL VOLTAGE REFERENCES
4.5 6.6 8.7
230 300 450
Self Bias
VRB
VRT - VRB
DIGITAL INPUTS
Short VRB and VRBS, Short VRT and VRTS
0.48 0.52 0.56
1.96 2.08 2.22
Digital Input Voltage
VIH
VIL
Digital Input Current
IIH
IIL
DIGITAL OUTPUTS
VDD = Max
VIH = VDD
VIL = 0V
4.0 -
-
- - 1.0
- -5
- -5
Digital Output Current
IOH
IOL
Digital Output Current
IOZH
IOZL
TIMING CHARACTERISTICS
OE = VSS, VDD = Min
OE = VDD, VDD = Max
VOH = VDD -0.5V
VOL = 0.4V
-1.1
3.7
-
-
VOH = VDD
VOL = 0V
--
--
-
-
16
16
Output Data Delay, tDL
POWER SUPPLY CHARACTERISTIC
- 18 30
Supply Current, IDD
CLAMP CHARACTERISTICS
fC = 20 MSPS, NTSC Ramp Wave Input
- 12 18
Clamp Offset Voltage, EOC
VIN = DC, PWS = 3µs
VREF = 0.5V
VREF = 2.5V
Clamp Pulse Width (Sync Pin Input), tCPW C = 100pF, R = 130kon Pin 15
Clamp Pulse Delay, tCPD
NOTE:
1. Electrical specifications guaranteed only under the stated operating conditions.
0 +20 +40
-50 -30 -10
1.75 2.75 3.75
- 25 -
UNIT
mA
V
V
V
V
µA
µA
mA
mA
µA
µA
ns
mA
mV
mV
µs
ns
4-4

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Timing Diagrams
CLOCK
ANALOG INPUT
tPW1 tPW0
N
DATA OUTPUT
N-3
HI1176
N+1
N-2
N-2
N-1
: POINT FOR ANALOG SIGNAL SAMPLING
tD = 18ns
FIGURE 1.
N+3
N
ANALOG INPUT
VI (1)
VI (2)
VI (3)
N+4
N+1
VI (4)
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
UPPER DATA
S (1)
C (1) S (2) C (2)
S (3) C (3)
S (4) C (4)
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATOR BLOCK A
LOWER DATA A
S (1)
H (1)
LD (-1)
C (1)
S (3)
H (3)
LD (1)
C (3)
LOWER COMPARATOR BLOCK B
LOWER DATA B
H (0)
C (0) S (2)
LD (-2)
H (2)
LD (0)
C (2)
S (4)
H (4)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
FIGURE 2.
OUT (0)
OUT (1)
4-5