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®
Data Sheet
April 10, 2007
ISL6423B
FN6412.1
Single Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6423B is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of singe antenna
ports. The device consists of a current-mode boost PWM
and a low-noise linear regulator along with the circuitry
required for 22kHz tone generation, modulation and I2C
device interface. The device makes the total LNB supply
design simple, efficient and compact with low external
component count.
The current-mode boost converters provides the linear
regulator with input voltage that is set to the final output
voltages, plus typically 0.8V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drop across the linear pass element while
permitting adequate voltage range for tone injection.
The final regulated output voltage is available at output
terminals to support the operation of an antenna port for
single tuners. The outputs for each PWM can be controlled
in two ways, full control from I2C using the VTOP and VBOT
bits or set the I2C to the lower range i.e., 13V/14V, and
switch to higher range i.e., 18V/19V, with the SELVTOP pin.
All the functions on this IC are controlled via the I2C bus by
writing 8 bits words onto the System Registers (SR). The
same register can be read back, and five I2C bits will report
the diagnostic status. Separate enable command sent on the
I2C bus provides for standby mode control for the PWM and
linear combination, disabling the output and forcing a shutdown
mode. The output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed to four levels.
The External modulation input EXTM can accept a
modulated Diseqc command and transfer it symmetrically to
the output. Alternatively the EXTM pin can be used to
modulate the continuos internal tone.
The FLT pin serves as an interrupt for the processor when
any condition turns OFF the LNB controller (Over
Temperature, Overcurrent, Disabled). The nature of the
Disable can be read of the I2C registers.
Features
• Single Chip Power solution
- Operation for 1-Tuner/1-Dish Applications
- Integrated DC/DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Selectable 13.3V or 18.3V Outputs
- Digital Cable Length Compensation (1V)
- I2C and Pin Controllable Output
• Output Back Bias Capability of 28V
• I2C Compatible Interface for Remote Device Control
• Registered Slave Address 0001 00XX
• 2.5V, 3.3V, 5V Logic Compatible
• External Pin to Toggle Between V and H Polarization
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
- External Modulation Input
• Internal Over-Temperature Protection and Diagnostics
• Internal OV, UV, Overload and Overtemp Flags
(Visible on I2C)
• FLT signal
• LNB Short-Circuit Protection and Diagnostics
• QFN, EPTSSOP Packages
• Pb-Free Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART
NUMBER*
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL6423BERZ 6423BERZ
(Note)
-20 to +85 24 Ld 4x4 QFN L24.4x4D
(Pb-free)
ISL6423BEVEZ ISL6423BEVEZ -20 to +85 28 Ld EPTSSOP M28.173B
(Note)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6423B
(28 LD EPTSSOP)
TOP VIEW
VCC 1
NC 2
FLT 3
SGND 4
SGND 5
TCAP 6
ADDR0 7
ADDR1 8
BYPASS 9
PGND 10
GATE 11
VSW 12
NC 13
CS 14
28 CPSWIN
27 CPSWOUT
26 CPVOUT
25 EXTM
24 SDA
23 SCL
22 TDOUT
21 TDIN
20 VO
19 NC
18 NC
17 AGND
16 SELVTOP
15 TXT
ISL6423B
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
SGND 1
18 EXTM
TCAP 2
17 SDA
ADDR0 3
16 SCL
ADDR1 4
15 TDOUT
BYPASS 5
14 TDIN
PGND 6
13 VO
7 8 9 10 11 12
2 FN6412.1
April 10, 2007

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Block Diagram
COUNTER
7 GATE
11
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF/BCF
DCL
PWM
LOGIC
Q
S
CLK1
OC1
PGND
6
CS
9
CS ILIM1
AMP
SLOPE
COMPENSATION
TDOUT
15
TONE
DECODER
14 TDIN
TXT
TTH
VREF1
8 VSW
13 VO
AGND
12
22 VCC
SGND
1
24 SGND
ON CHIP
LINEAR
UVLO
POR
SOFT-START
INT 5V
SOFT-START
EN1/EN2
NOTE:
5
1. Pinouts shown are for the QFN package.
10
17 16
34
23
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ1
SDA SCL
ISELL&H
EN
ENT
ADDR0
OUVF
ADDR1
OLF/BCF
OTF
I2C
INTERFACE
TTH
VTOP VBOT
DCL
CLK1 OSC.
BGV
DIV &
WAVE SHAPING
TONE
INJ
CKT
INT
TONE
THERMAL
SHUTDOWN
+
-
EXT TONE CKT
ENT1
CHARGE PUMP
CPVOUT
2 18
20 21
19

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Typical Application Schematic QFN
C27 0.22µF
C23
56µF
0
0
R10
18
C26 1µF
0
2
L5
15µH
1
D5
CMS06
TPC6002
Q2
R9
470
R8 C21
0.1 100pF
C22
56µF
0
00
L6 4.7µH
12
C18
10µF
C19
10µF
00
C20
10µF
0
C24
1µF
0
C29
1n C25 47n
0
1
2
3
4
5
6
SGND
TCAP
ADDR0
U2
ADDR1 ISL6423ER
BYPASS
PGND
EXTM
SDA
SCL
TDOUT
TDIN
VO
18
17
16
15
14
13
C16
10n
D7 CMS06
0
R11 100
R12 100
D6
CMS06
C28
0.1µF
R23
10k
L4 220µH
12
C15 0.22µF
R7 15
M6
NDS356AP
R24
4.7k
R13 4.7k
R22
47k
Q4
2N2222A
VIN
RTN
FLT BAR
EXTM
SDA
SCL
VLNB
D8
1.5KE24
RTN
TXT
TDOUT
SELVTOP
NOTE : SDA and SCL require pull up to the required logic level.

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Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN 1 and 2, SEL18V 1 and 2) . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 2, 3) θJA (°C/W) θJC (°C/W)
QFN Package (Notes 2, 3) . . . . . . . . . .
38
4.5
EPTSSOP Package (Notes 2, 3) . . . . .
35
2.5
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -40°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . -20°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may
trigger the shutdown of the device even before +150°C, since this number is specified as typical.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN = H, VTOP
VBOT = L, ENT = L, DCL = L, IOUT = 12mA, unless otherwise noted. See software description section for I2C
access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN = L
- 1.5 3.0 mA
Supply Current
UNDERVOLTAGE LOCKOUT
IIN EN = VTOP = VBOT = ENT = H, No Load
-
4.0 8.0
mA
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 5)
(Note 5)
- 8196 - Cycles
Output Voltage (Note 5)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VO1
VO1
VO1
VO1
DVO1,
DVO2
DVO1,
DVO2
IMAX
(Refer to Table 1)
(Refer to Table 1)
(Refer to Table 1)
(Refer to Table 1)
VIN = 8V to 14V; VO = 13.3V
VIN = 8V to 14V; VO = 18.3V
IO = 0mA to 350mA
IO = 0mA to 750mA
DCL = 0, ISEL H = 0, ISEL L = 0 (Note 8)
DCL = 0, ISEL H = 0, ISEL L = 1 (Note 8)
13.04 13.3 13.56
14.02 14.3 14.58
17.94 18.3 18.66
19.00 19.3 19.68
- 4.0 40.0
- 4.0 60.0
- 50 80
- 100 200
275 305 345
515 570 630
V
V
V
V
mV
mV
mV
mV
mA
mA
DCL = 0, ISEL H = 1, ISEL L = 0 (Note 8)
635 705 775
mA
DCL = 0, ISEL H = 1, ISEL L = 1 (Note 8)
800 890 980
mA
Dynamic Overload Protection Off Time TOFF DCL = 0, Output Shorted (Note 8)
- 900 -
ms
Dynamic Overload Protection On Time
TON
- 51 -
ms
Static Output Current Limiting
Cable Fault CABF Threshold
IMAX
ICAB
DCL = 1 (Note 8)
EN = 1, VO = 19V, No Tone.
- 1000 -
2 10 20
mA
mA
5 FN6412.1
April 10, 2007