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®
Data Sheet
March 12, 2007
ISL6540A
FN6288.2
Single-Phase Buck PWM Controller with
Integrated High Speed MOSFET Driver
and Pre-Biased Load Capability
The ISL6540A is an improved version of the ISL6540
single-phase voltage-mode PWM controller with input voltage
feedforward compensation to maintain a constant loop gain for
optimal transient response, especially for applications with a
wide input voltage range. Its integrated high speed
synchronous rectified MOSFET drivers and other sophisticated
features provide complete control and protection for a DC/DC
converter with minimum external components, resulting in
minimum cost and less engineering design efforts.
The output voltage of the converter can be precisely regulated
with an internal reference voltage of 0.591V, and has an
improved system tolerance of ±0.68% over commercial
temperature and line load variations. An external voltage can
be used in place of the internal reference for voltage
tracking/DDR applications.
The ISL6540A has an internal linear regulator or external linear
regulator drive options for applications with only a single supply
rail. The internal oscillator is adjustable from 250kHz to 2MHz.
The integrated voltage margining, programmable pre-biased
soft-start, differential remote sensing amplifier, and
programmable input voltage POR features enhance the
ISL6540A value.
Pinout
ISL6540A
(28 LD 5x5 QFN)
TOP VIEW
28 27 26 25 24 23 22
VSEN+ 1
21 BOOT
VSEN- 2
20 UGATE
REFOUT 3
REFIN 4
SS 5
GND
BOTTOM
SIDE PAD
19 PHASE
18 PGND
17 LGATE
OFS+ 6
16 PVCC
OFS- 7
15 LINDRV
8 9 10 11 12 13 14
Features
• VIN and Power Rail Operation from +3.3V to +20V
• Fast Transient Response - 0 to 100% Duty Cycle
- 15MHz Bandwidth Error Amplifier with 6V/μs Slew Rate
- Voltage-Mode PWM Leading and Trailing-Edge
Modulation Control
- Input Voltage Feedforward Compensation
• 2.9V to 5.5V High Speed 2A/4A MOSFET Gate Drivers
- Tri-state for Power Stage Shutdown
• Internal Linear Regulator (LR) - 5.5V Bias from VIN
• External LR Drive for Optimal Thermal Performance
• Voltage Margining with Independently Adjustable Upper and
Lower Settings for System Stress Testing & Over Clocking
• Reference Voltage I/O for DDR/Tracking Applications
• Improved 0.591V Internal Reference with Buffered Output
- ±0.68%/±1.0% Over Commercial/Industrial Range
• Source and Sink Overcurrent Protections
- Low- and High-Side MOSFET rDS(ON) Sensing
• Overvoltage and Undervoltage Protections
• Small Converter Size - QFN package
• Oscillator Programmable from 250kHz to 2MHz
• Differential Remote Voltage Sensing with Unity Gain
• Programmable Soft-Start with Pre-Biased Load Capability
• Power Good Indication with Programmable Delay
• EN Input with Voltage Monitoring Capability
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply for some Microprocessors and GPUs
• Wide and Narrow Input Voltage Range Buck Regulators
• Point of Load Applications
• Low-Voltage and High Current Distributed Power Supplies
Ordering Information
PART
NUMBER*
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-Free) DWG. #
ISL6540ACRZ ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5
ISL6540ACRZA ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5
ISL6540AIRZ ISL6540AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
ISL6540AIRZA ISL6540AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
ISL6540A
2 FN6288.2
March 12, 2007

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ISL6540A
Typical Application I (Internal Linear Regulator with Remote Sense)
+3.3V to +20V
RVIN
CF1
RCC
LIN DBOOT
CF2
RBOOT
CHFIN
CBIN
RVFF
VCC
PVCC
VIN Internal 5.6V Bias
Linear Regulator
VFF
BOOT
HSOC
RHSOC
CF3 CVFF
VCC
EN
REFIN
REFOUT
PG
CPG_DLY PG_DLY
RFS FS
ISL6540A
UGATE
CHSOC
PHASE
LGATE
PGND
LSOC RLSOC
CLSOC
COMP
Q1
Q2
CBOOT
LOUT
CHFOUT
MARCTRL
ROFS+
RMARG
ROFS-
OFS+
OFS-
CSS
SS
C1
FB
VMON
VSEN+
C2
ZFB
R2
LINDRV
GND GND
VSEN-
C3 R3
R1 ZIN
CSEN
RFB
ROS
VOUT
CBOUT
10Ω 10Ω
VSENSE+
VSENSE-
3 FN6288.2
March 12, 2007

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ISL6540A
Typical Application II (External Linear Regulator without Remote Sense)
+3.3V to +20V
RDRV
RVIN
CLC RLC
LINDRV
CF3
RVFF
VIN
CVFF
VCC
VFF
REFOUT
REFIN
EN
PG
CPG_DLY
PG_DLY
RFS FS
ROFS+
MARCTRL
OFS+
CF1 RCC
VCC
ISL6540A
LIN DBOOT
CF2
RBOOT
PVCC
BOOT
HSOC
RHSOC
CHFIN
UGATE
CHSOC
Q1
PHASE
LGATE
PGND
LSOC
RLSOC
Q2
CLSOC
COMP
C1
FB
ZFB
C2
R2
CBIN
CBOOT
LOUT
CHFOUT
C3 R3
ZIN
R1
RMARG
ROFS-
OFS-
CSS
SS
GND GND
VMON
VCC
VSEN+
VSEN-
ROS
Rvmon1
RvmonOS
VOUT
CBOUT
4 FN6288.2
March 12, 2007

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ISL6540A
Typical Application III (Dual Data Rate I or II)
VDDQ
1.8V or 2.5V
5V
CVFF
REN1
RVFF
CF1
VIN
VFF
EN
LIN
RCC
DBOOT
CF2
VCC
PVCC
BOOT
HSOC
RHSOC
REN2
CF4
1K
15nF
REFIN
REFOUT
1K DIMM
PG
CPG_DLY
PG_DLY
RFS
FS
ISL6540A
UGATE
CHSOC
PHASE
LGATE
PGND
LSOC
RLSOC
COMP CLSOC
CHFIN
Q1
Q2
CBIN
CBOOT
LOUT
CHFOUT
ROFS+
MARCTRL
OFS+
RMARG
ROFS-
OFS-
CSS
SS
ZFB
C1
FB
VMON
VSEN+
C2
R2
VSEN-
C3 R3
R1 ZIN
CSEN
RFB
LINDRV GND GND
VTT
1.25V (DDR I)
0.9V (DDR II)
CBOUT
5 FN6288.2
March 12, 2007