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®
Data Sheet
ISL6610, ISL6610A
November 22, 2006
FN6395.0
Dual Synchronous Rectified MOSFET
Drivers
The ISL6610, ISL6610A integrates two ISL6609, ISL6609A
drivers with enable function removed and is optimized to
drive two independent power channels in a synchronous-
rectified buck converter topology. These drivers, combined
with an Intersil ISL63xx or ISL65xx multiphase PWM
controller, form a complete high efficiency voltage regulator
at high switching frequency.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
The ISL6610, ISL6610A features 4A typical sink current for
the lower gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the lower
MOSFET due to the high dV/dt of the switching node.
The ISL6610, ISL6610A also features an input that
recognizes a high-impedance state, working together with
Intersil multiphase PWM controllers to prevent negative
transients on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
In addition, the ISL6610As bootstrap function is designed to
prevent the BOOT capacitor from overcharging, should
excessively large negative swings occur at the transitions of
the PHASE node.
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
Features
• 5V Quad N-Channel MOSFET Drives for Two
Synchronous Rectified Bridges
• Pin-to-pin Compatible with ISL6614 (12V Drive)
• Adaptive Shoot-Through Protection
• 0.4Ω On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
- Fast Output Rise and Fall
- Low Tri-State Hold-Off Time
• BOOT Capacitor Overcharge Prevention (ISL6610A)
• Low VF Internal Bootstrap Diode
• Power-On Reset
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
(Note)
ISL6610CBZ
PART
MARKING
6610CBZ
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
0 to +70 14 Ld SOIC
PKG.
DWG. #
M14.15
ISL6610CRZ 66 10CRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610IBZ 6610IBZ -40 to +85 14 Ld SOIC M14.15
ISL6610IRZ 66 10IRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
ISL6610ACBZ 6610ACBZ 0 to +70 14 Ld SOIC M14.15
ISL6610ACRZ 66 10ACRZ 0 to +70 16 Ld 4x4 QFN L16.4x4
ISL6610AIBZ 6610AIBZ -40 to +85 14 Ld SOIC M14.15
ISL6610AIRZ 66 10AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.

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ISL6610, ISL6610A
Pinouts
ISL6610, ISL6610A
(14 LD SOIC)
TOP VIEW
PWM1 1
PWM2 2
GND 3
LGATE1 4
PVCC 5
PGND 6
LGATE2 7
14 VCC
13 PHASE1
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
8 PHASE2
ISL6610, ISL6610A
(16 LD QFN)
TOP VIEW
16 15 14 13
GND 1
LGATE1 2
PVCC 3
PGND 4
17
GND
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
5678
Block Diagram
ISL6610, ISL6610A
VCC
PVCC
RBOOT
BOOT1
UGATE1
4.9K
PWM1
4.6K
VCC
4.9K
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
PVCC
PGND
RBOOT
PWM2
GND
4.6K
SHOOT-
THROUGH
PROTECTION
PHASE1
CHANNEL 1
LGATE1
PGND
BOOT2
UGATE2
PHASE2
CHANNEL 2
PVCC
LGATE2
PGND
PAD FOR ISL6610CR/10ACR, THE PAD ON THE BOTTOM SIDE OF
THE QFN PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
INTEGRATED 3Ω RESISTOR (RBOOT) AVAILABLE ONLY IN ISL6610A
2 FN6395.0
November 22, 2006

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ISL6610, ISL6610A
Typical Application - Multiphase Converter Using ISL6610 Gate Drivers
+5V
VCC
BOOT1
UGATE1
PHASE1
PGOOD
EN
VID
+5V
FB COMP
VSEN
VCC
ISEN1
PWM1
PWM2
MAIN ISEN2
CONTROL
ISL65xx
DUAL
DRIVER
ISL6610
LGATE1
PVCC
+5V
BOOT2
PWM1
PWM2
GND
UGATE2
PHASE2
NC2
LGATE2
NC1
PGND
ISEN3
FS/DIS
PWM3
PWM4
GND ISEN4
+5V
VCC
BOOT1
UGATE1
PHASE1
LGATE1
DUAL
DRIVER
ISL6610
PVCC
+5V
BOOT2
PWM1
PWM2
GND
UGATE2
PHASE2
LGATE2
PGND
+12V
+12V
+12V
+12V
3
+VCORE
FN6395.0
November 22, 2006

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ISL6610, ISL6610A
Absolute Maximum Ratings
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10μJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical)
θJA(°C/W) θJC(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
90
N/A
QFN Package (Notes 2 and 3). . . . . . .
46
8.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at 150°C may shorten the life of the part.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3. θJC, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications These specifications apply for TA = -40°C to +85°C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
SUPPLY CURRENT
Bias Supply Current
BOOTSTRAP DIODE
IVCC+PVCC PWM pin floating, VVCC = VPVCC = 5V
FPWM = 300kHz, VVCC = VPVCC = 5V
- 240 -
μA
- 1.6 - mA
Forward Voltage
VF Forward bias current = 2mA
TA = 0°C to +70°C
0.30 0.60 0.70
V
POWER-ON RESET
Forward bias current = 2mA
TA = -40°C to +85°C
0.30 0.60 0.75
V
POR Rising
- 3.4 4.2 V
POR Falling
2.6 3.0
-
V
Hysteresis
- 400 - mV
PWM INPUT
Sinking Impedance
Source Impedance
Tri-State Rising Threshold
Tri-State Falling Threshold
Tri-State Shutdown Holdoff Time
SWITCHING TIME (Note 4, See Figure 1)
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
RPWM_SNK
RPWM_SRC
VVCC = VPVCC = 5V (250mV Hysteresis)
VVCC = VPVCC = 5V(300mV Hysteresis)
tTSSHD
tRU
tRL
tFU
tFL
tPDLU
tPDLL
3nF Load
3nF Load
3nF Load
3nF Load
Outputs Unloaded
Outputs Unloaded
- 4.6 -
- 4.9 -
1.00 1.20 1.40
3.10 3.41 3.70
- 80 -
- 8.0 -
- 8.0 -
- 8.0 -
- 4.0 -
- 18 -
- 25 -
kΩ
kΩ
V
V
ns
ns
ns
ns
ns
ns
ns
4 FN6395.0
November 22, 2006

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ISL6610, ISL6610A
Electrical Specifications These specifications apply for TA = -40°C to +85°C, unless otherwise noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
tPDHU
tPDHL
tPTS
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
- 18
- 23
- 20
Upper Drive Source Resistance
RUG_SRC 250mA Source Current
Upper Drive Sink Resistance
RUG_SNK 250mA Sink Current
Lower Drive Source Resistance
RLG_SRC 250mA Source Current
Lower Drive Sink Resistance
RLG_SNK 250mA Sink Current
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
- 1.0
- 1.0
- 1.0
- 0.4
MAX
-
-
-
2.5
2.5
2.5
1.0
UNITS
ns
ns
ns
Ω
Ω
Ω
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 15 PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
2 16 PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3 1 GND Bias and reference ground. All signals are referenced to this node.
4 2 LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
5 3 PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
6 4 PGND Power ground return of both low gate drivers.
- 5,8 NC1,2 No connection.
7 6 LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
8 7 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9 9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10 10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11 11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12 12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13 13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14 14 VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
- 17 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6395.0
November 22, 2006