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® NOT RDENaSCtEaEOWESMDhIMSEeELeS1NtIG2D0NE2SD8 FOR
X1228
4K (512 x 8), 2-WireRTC
May 18, 2006
FN8100.4
Real Time Clock/Calendar/CPU
Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to
±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
www.DataSheet4U.com
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C*
— 400kHz Data Transfer Rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz, or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 14 Ld SOIC and 14 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X1228
Ordering Information
PART NUMBER
X1228S14-4.5A
X1228S14Z-4.5A (Note)
X1228S14I-4.5A
PART
MARKING
X1228S AL
X1228S ZAL
X1228S AM
VCC RANGE
(V)
2.7 to 5.5
VTRIP
4.63V ± 112mV
TEMP RANGE
(°C)
PACKAGE
0 to 70
14 Ld SOIC
0 to 70
14 Ld SOIC (Pb-free)
-40 to 85 14 Ld SOIC
PKG. DWG. #
MDP0027
MDP0027
MDP0027
X1228S14IZ-4.5A (Note) X1228S ZAM
-40 to 85 14 Ld SOIC (Pb-free)
MDP0027
X1228V14-4.5A
X1228V AL
0 to 70
14 Ld TSSOP
M14.173
X1228V14Z-4.5A (Note) X1228V ZAL
0 to 70
14 Ld TSSOP (Pb-free) M14.173
X1228V14I-4.5A
X1228V AM
-40 to 85 14 Ld TSSOP
M14.173
X1228V14IZ-4.5A (Note) X1228V ZAM
-40 to 85 14 Ld TSSOP (Pb-free) M14.173
X1228S14
X1228S
4.38V ± 112mV
0 to 70
14 Ld SOIC
MDP0027
X1228S14Z (Note)
X1228S Z
0 to 70
14 Ld SOIC (Pb-free)
MDP0027
X1228S14I
X1228S I
-40 to 85 14 Ld SOIC
MDP0027
X1228S14IZ (Note)
X1228S ZI
-40 to 85 14 Ld SOIC (Pb-free)
MDP0027
X1228V14
X1228V
0 to 70
14 Ld TSSOP
M14.173
X1228V14Z (Note)
X1228V Z
0 to 70
14 Ld TSSOP (Pb-free) M14.173
X1228V14I
X1228V I
-40 to 85 14 Ld TSSOP
M14.173
X1228V14IZ (Note)
X1228V ZI
-40 to 85 14 Ld TSSOP (Pb-free) M14.173
X1228S14-2.7A
X1228S AN
2.85V ± 100mV
0 to 70
14 Ld SOIC
MDP0027
X1228S14Z-2.7A (Note) X1228S ZAN
0 to 70
14 Ld SOIC (Pb-free)
MDP0027
X1228S14I-2.7A
X1228S AP
-40 to 85 14 Ld SOIC
MDP0027
X1228S14IZ-2.7A (Note) X1228S ZAP
-40 to 85 14 Ld SOIC (Pb_free)
MDP0027
X1228V14-2.7A
X1228V AN
0 to 70
14 Ld TSSOP
M14.173
X1228V14Z-2.7A (Note) X1228V ZAN
0 to 70
14 Ld TSSOP (Pb-free) M14.173
X1228V14I-2.7A
X1228V AP
-40 to 85 14 Ld TSSOP
M14.173
X1228V14IZ-2.7A (Note) X1228V ZAP
-40 to 85 14 Ld TSSOP (Pb-free) M14.173
X1228S14-2.7*
X1228S F
2.65V ± 100mV
0 to 70
14 Ld SOIC
MDP0027
X1228S14Z-2.7* (Note)
X1228S ZF
0 to 70
14 Ld SOIC (Pb-free)
MDP0027
X1228S14I-2.7
X1228S G
-40 to 85 14 Ld SOIC
MDP0027
X1228S14IZ-2.7 (Note)
X1228S ZG
-40 to 85 14 Ld SOIC (Pb-free)
MDP0027
X1228V14-2.7
X1228V F
0 to 70
14 Ld TSSOP
M14.173
X1228V14Z-2.7 (Note)
X1228V ZF
0 to 70
14 Ld TSSOP (Pb-free) M14.173
X1228V14I-2.7
X1228V G
-40 to 85 14 Ld TSSOP
M14.173
X1228V14IZ-2.7 (Note)
X1228V ZG
-40 to 85 14 Ld TSSOP (Pb-free) M14.173
*Add "T1" suffix for tape and reel.
Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2 FN8100.4
May 18, 2006

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X1228
PIN DESCRIPTIONS
14 Ld TSSOP/SOIC
X1
X2
NC
NC
NC
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 VBACK
12 PHZ/IRQ
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP Symbol
1 X1
2 X2
6 RESET
7 VSS
8 SDA
9 SCL
12 PHZ/IRQ
13 VBACK
14 VCC
Brief Description
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X1 are highly
recommended. See Application section for more recommendations.
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X2 are highly
recommended. See Application section for more recommendations.
RESET Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped below
a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the
pullup resistor is 5kΩ. If unused, tie to ground.
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls the
fall time of the output signal with the use of a slope controlled pull-down. The circuit is
designed for 400kHz 2-wire interface speeds.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The
input buffer on this pin is always active (not gated).
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from the
internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on
page 14.
VBACK. This input provides a backup supply voltage to the device. VBACK supplies power
to the device in the event the VCC supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
VCC.
3 FN8100.4
May 18, 2006