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®
Data Sheet
April 14, 2006
X1288
FN8102.3
2-WireRTC Real Time
Clock/Calendar/CPU Supervisor with
EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and
Hundredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital-frequency adjustment setting to
±30ppm
• CPU Supervisor Functions
— Power-on Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
www.DataSheet4U.com — 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
BLOCK DIAGRAM
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 16-Lead SOIC and 14-Lead TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C is a trademark of Philips. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X1288
PIN DESCRIPTIONS
X1
X2
NC
NC
NC
NC
RESET
VSS
16 Ld SOIC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
VBACK
PHZ/IRQ
NC
NC
NC
SCL
SDA
14 Ld TSSOP
X1
X2
NC
NC
NC
RESET
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
VBACK
PHZ/IRQ
NC
NC
SCL
SDA
NC = No internal connection
Ordering Information
PART NUMBER
X1288S16-4.5A*
X1288S16I-4.5A*
X1288V14-4.5A*
X1288V14Z-4.5A* (Note)
X1288V14I-4.5A*
X1288V14IZ-4.5A* (Note)
PART MARKING
X1288S AL
X1288S AM
X1288V AL
X1288V ZAL
X1288V AM
X1288V ZAM
VCC RANGE (V)
4.5 to 5.5
VTRIP RANGE
4.63V±112mV
OPERATING
TEMP RANGE (°C)
0 to 70
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
PACKAGE
16 Ld SOIC
16 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
X1288S16*
X1288S16I*
X1288V14*
X1288V14Z* (Note)
X1288V14I*
X1288V14IZ* (Note)
X1288S
X1288S I
X1288V
X1288V Z
X1288V I
X1288V ZI
4.38V±112mV
0 to 70
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
16 Ld SOIC
16 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
X1288S16-2.7A*
X1288S16I-2.7A*
X1288V14-2.7A*
X1288V14Z-2.7A* (Note)
X1288V14I-2.7A*
X1288V14IZ-2.7A* (Note)
X1288S16-2.7*
X1288S16I-2.7*
X1288V14-2.7*
X1288V14Z-2.7* (Note)
X1288V14I-2.7*
X1288V14IZ-2.7* (Note)
X1288S AN
X1288S AP
X1288V AN
X1288V ZAN
X1288V AP
X1288V ZAP
X1288S F
X1288S G
X1288V F
X1288V ZF
X1288V G
X1288V ZG
2.7 to 5.5
2.85V±100mV
2.65V±100mV
0 to 70
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
0 to 70
-40 to +85
0 to 70
0 to 70
-40 to +85
-40 to +85
16 Ld SOIC
16 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
16 Ld SOIC
16 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2 FN8102.3
April 14, 2006

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X1288
PIN ASSIGNMENTS
Pin Number
SOIC TSSOP Symbol
Brief Description
1 1 X1 X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1288 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X1 are highly recommended. See Application section for more information.
2 2 X2 X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1288 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X2 are highly recommended. See Application section for more information.
7 6 RESET RESET Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped
below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended
value for the pullup resistor is 5k. If unused, tie to ground.
8
7
VSS
VSS.
9 8 SDA Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speed.
10 9 SCL Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
14 12 PHZ/IRQ Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from
the internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 100Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of
the Clock Control Memory map. See “Programmable Frequency Output Bits - FO1,
FO0” on page 13.
15 13 VBACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
16
14
VCC
VCC.
3 FN8102.3
April 14, 2006