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®
Data Sheet
X28C010, X28HT010
February 12, 2007
FN8105.1
5V, Byte Alterable EEPROM
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
www.DataSheet4U.com
Features
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Writecell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• X28HT010 is fuly functional @ +175°C
Pinouts
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
CERDIP
Flat Pack
SOIC (R)
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 X28C010 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PGA
15I/O0 17I/O2 19I/O3 21I/O5 22I/O6
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
12A2 11A3
25A10
OE
26
10A4
9A5
X28C010
(Bottom View)
27A11
A
28
9
8A6 7A7
29A8
A
30
13
A12 A15 NC VCC NC NC A 14
6 5 2 36 34 32 31
4A16
NC
3
NC WE NC
1 35 33
EXTENDED LCC
4 3 2 32 31 30
A7 5
A6 6
A5 7
1
29 A14
28 A13
27 A8
A4
A3
A2
8
9
10
X28C010
(Top View)
26
25
24
A9
A11
OE
A1 11
23 A10
A0 12
22 CE
I/O 0 13
21 I/O7
14 15 16 17 18 19 20
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Ordering Information
PART NUMBER
X28C010D-12
X28C010D-15
X28C010DI
X28C010DI-12
X28C010DI-15
X28C010DM
X28C010DM-12
X28C010DM-15
X28C010DMB-12
X28C010DMB-15
X28C010DMB-20
X28C010FI-12
X28C010FI-15
X28C010FI-20
X28C010FM
X28C010FM-12
X28C010FMB-12
X28C010FMB-15
X28C010K-25
X28C010KM-12
X28C010KM-25
X28C010KMB-12
X28C010KMB-15
X28C010NM-12
X28C010NM-15
X28C010NMB-12
X28C010NMB-15
X28C010RI-12
X28C010RI-20
X28C010RI-20T1
X28C010RM-15
X28C010RMB-25
X28HT010W
PART MARKING
X28C010D-12
X28C010D-15
X28C010DI
X28C010DI-12
X28C010DI-15
X28C010DM
X28C010DM-12
X28C010DM-15
C X28C010DMB-12
C X28C010DMB-15
C X28C010DMB-20
X28C010FI-12
X28C010FI-15
X28C010FI-20
X28C010FM
X28C010FM-12
C X28C010FMB-12
C X28C010FMB-15
X28C010K-25
X28C010KM-12
X28C010KM-25
C X28C010KMB-12
C X28C010KMB-15
X28C010NM-12
X28C010NM-15
C X28C010NMB-12
C X28C010NMB-15
X28C010RI-12
X28C010RI-20
X28C010RI-20
X28C010RM-15
C X28C010RMB-25
X28C010, X28HT010
ACCESS
TIME
120ns
150ns
-
120ns
150ns
-
120ns
150ns
120ns
150ns
200ns
120ns
150ns
200ns
-
120ns
120ns
150ns
250ns
120ns
250ns
120ns
150ns
120ns
150ns
120ns
150ns
120ns
200ns
200ns
150ns
250ns
200ns
TEMP RANGE
(°C)
PACKAGE
PKG. DWG #
0 to +70
32-Ld Cerdip
F32.6
0 to +70
32-Ld Cerdip
F32.6
-40 to +85 32-Ld Cerdip
F32.6
-40 to +85 32-Ld Cerdip
F32.6
-40 to +85 32-Ld Cerdip
F32.6
-55 to +125 32-Ld Cerdip
F32.6
-55 to +125 32-Ld Cerdip
F32.6
-55 to +125 32-Ld Cerdip
F32.6
MIL-STD-883 32-Ld Cerdip
F32.6
MIL-STD-883 32-Ld Cerdip
F32.6
MIL-STD-883 32-Ld Cerdip
-40 to +85 32-Ld Flat Pack
-40 to +85 32-Ld Flat Pack
-40 to +85 32-Ld Flat Pack
-55 to +125 32-Ld Flat Pack
-55 to +125 32-Ld Flat Pack
MIL-STD-883 32-Ld Flat Pack
MIL-STD-883 32-Ld Flat Pack
0 to +70
36-Ld Pin Grid Array
G36.760x760A
-55 to +125 36-Ld Pin Grid Array
G36.760x760A
-55 to +125 36-Ld Pin Grid Array
G36.760x760A
MIL-STD-883 36-Ld Pin Grid Array
G36.760x760A
MIL-STD-883 36-Ld Pin Grid Array
G36.760x760A
-55 to +125 32-Ld Extended LCC
-55 to +125 32-Ld Extended LCC
MIL-STD-883 32-Ld Extended LCC
MIL-STD-883 32-Ld Extended LCC
-40 to +85 32-Ld Ceramic SOIC (Gull Wing)
-40 to +85 32-Ld Ceramic SOIC (Gull Wing)
-40 to +85 32-Ld Ceramic SOIC (Gull Wing)
-55 to +125 32-Ld Ceramic SOIC (Gull Wing)
MIL-STD-883 32-Ld Ceramic SOIC (Gull Wing)
-40 to +175 Wafer
2 FN8105.1
February 12, 2007

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Block Diagram
X28C010, X28HT010
A8-A16
X Buffers
Latches and
Decoder
1Mbit
EEPROM
Array
A0-A7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
CE Control
OE Logic and
WE Timing
VCC
VSS
Pin Descriptions
Addresses (A0-A16)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C010/X28HT010
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010/X28HT010.
Back Bias Voltage (VBB) (X28HT010 only)
It is required to provide -3V on pin 1. This negative voltage
improves higher temperature functionality.
I/O0-I/O7
Data Inputs/Outputs
Pin Names
SYMBOL
A0-A16
I/O0-I/O7
WE
CE
OE
VCC
VSS
NC
VBB*
*VBB applies to X28HT010 only.
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
-3V
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010/X28HT010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
3 FN8105.1
February 12, 2007

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X28C010, X28HT010
Page Write Operation
The page write feature of the X28C010/X28HT010 allows
the entire memory to be written in 5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28C010/X28HT010 prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A8 through A16) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW transition,
must begin within 100µs of the falling edge of the preceding
WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100µs.
Write Operation Status Bits
The X28C010/X28HT010 provides the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling I/O7
Last
WE Write
I/O DP TB 5 4 3 2 1 0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The X28C010/X28HT010 features DATA Polling as a
method to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
X28C010/X28HT010, eliminating additional interrupt inputs
or external hardware. During the internal programming cycle,
any attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx xxxx,
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data. Note: If the
X28C010/X28HT010 is in the protected state, and an illegal
write operation is attempted, DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C010/X28HT010 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
cease and the device will be accessible for additional read or
write operations.
CE
OE
VIH
I/O7
A0-A14
An
HIGH Z
VOL
An An An An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
VOH
X28C010
Ready
An
4 FN8105.1
February 12, 2007

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Write Data
Writes
Complete?
Yes
Save Last Data
and Address
No
X28C010, X28HT010
DATA Polling can effectively halve the time for writing to the
X28C010/X28HT010. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
Read Last
Address
IO7
Compare?
Yes
X28C010
Ready
No
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O6
Last
WE Write
CE
OE
I/O6
VOH
*
VOL
HIGH Z
*
* Beginning and ending state of I/O6 will vary
FIGURE 4. TOGGLE BIT BUS SEQUENCE
X28C010
Ready
5 FN8105.1
February 12, 2007