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®
Data Sheet
X28C512, X28C513
June 7, 2006
FN8106.2
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 support a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C513 support the software data
protection option.
www.DataSheet4U.com
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or VPP control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
• Highly Reliable Direct WriteCell
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
- DATA polling
- Toggle bit polling
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
A7-A15
X28C512, X28C513
X Buffers
Latches and
Decoder
512Kbit
EEPROM
Array
A0-A6
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
Ordering Information
PART NUMBER
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12*
X28C512JZ-12* (See Note)
X28C512JI-12
X28C512JIZ-12* (See Note)
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12*
X28C513JZ-12* (Note)
X28C513JI-12*
X28C513JIZ-12* (Note)
X28C513JM-12
CE
OE
WE
VCC
VSS
Control
Logic and
Timing
I/O0-I/O7
Data Inputs/Outputs
PART MARKING
X28C512D
X28C512DM
X28C512J
X28C513EM
X28C512D-12
X28C512DI-12
X28C512DMB-12
X28C512FMB-12
X28C512J-12
X28C512J-12 Z
X28C512JI-12
X28C512JI-12 Z
X28C512JM-12
X28C512KM-12
X28C512PI-12
X28C512RMB-12
X28C513EM-12
X28C513EMB-12
X28C513J-12
X28C513J-12 Z
X28C513JI-12
X28C513JI-12 Z
X28C513JM-12
ACCESS TIME
(ns)
-
120
TEMP RANGE (°C)
0 to +70
-55 to +125
0 to +70
-55 to +125
0 to +70
-40 to +85
Mil-STD-883
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
-55 to +125
-40 to +85
Mil-STD-883
-55 to +125
Mil-STD-883
0 to +70
0 to +70
-40 to +85
-40 to +85
-55 to +125
PACKAGE
32 Ld CERDIP
32 Ld CERDIP
32 Ld PLCC
32 Ld LCC
32 Ld CERDIP
32 Ld CERDIP
32 Ld CERDIP
32 Ld Flat Pack
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
36 Ld CPGA
32 Ld PDIP
32 Ld Flat Pack
32 Ld LCC
32 Ld LCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC
2 FN8106.2
June 7, 2006

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X28C512, X28C513
Ordering Information (Continued)
PART NUMBER
X28C512D-15
PART MARKING
X28C512D-15
ACCESS TIME
(ns)
150
TEMP RANGE (°C)
0 to +70
PACKAGE
32 Ld CERDIP
X28C512DI-15
X28C512DMB-15
X28C512DI-15
X28C512DMB-15
-40 to +85
Mil-STD-883
32 Ld CERDIP
32 Ld CERDIP
X28C512J-15*
X28C512J-15
0 to +70
32 Ld PLCC
X28C512JZ-15* (See Note)
X28C512JI-15*
X28C512J-15 Z
X28C512JI-15
0 to +70
-40 to +85
32 Ld PLCC (Pb-free)
32 Ld PLCC
X28C512JIZ-15* (See Note)
X28C512JM-15
X28C512JI-15 Z
X28C512JM-15
-40 to +85
-55 to +125
32 Ld PLCC (Pb-free)
32 Ld PLCC
X28C513EM-15
X28C513EM-15
-55 to +125
32 Ld LCC
X28C513EMB-15
X28C513J-15*
X28C513EMB-15
X28C513J-15
Mil-STD-883
0 to +70
32 Ld LCC
32 Ld PLCC
X28C513JZ-15* (Note)
X28C513J-15 Z
0 to +70
32 Ld PLCC (Pb-free)
X28C513JI-15
X28C513JI-15
-40 to +85
32 Ld PLCC
X28C513JIZ-15* (Note)
X28C513JI-15 Z
-40 to +85
32 Ld PLCC (Pb-free)
X28C513JM-15
X28C512DMB-20
X28C513JM-15
X28C512DMB-20
200
-55 to +125
Mil-STD-883
32 Ld PLCC
32 Ld CERDIP
X28C512JM-20
X28C512JM-20
-55 to +125
32 Ld PLCC
X28C512KI-20
X28C512KM-20
X28C512KI-20
X28C512KM-20
-40 to +85
-55 to +125
36 Ld CPGA
36 Ld CPGA
X28C513EI-20
X28C513EM-20
X28C513EI-20
X28C513EM-20
-40 to +85
-55 to +125
32 Ld LCC
32 Ld LCC
X28C513EMB-20
X28C513EMB-20
Mil-STD-883
32 Ld LCC
X28C513J-20T1
X28C512EM-25
X28C513J-20
X28C512EM-25
250
0 to +70
-55 to +125
32 Ld PLCC Tape and Reel
32 Ld LCC
X28C512JM-25
X28C512KM-25
X28C512JM-25
X28C512KM-25
-55 to +125
-55 to +125
32 Ld PLCC
36 Ld CPGA
X28C512KMB-25
X28C512KMB-25
Mil-STD-883
36 Ld CPGA
X28C513EM-25
X28C513EMB-25
X28C513EM-25
X28C513EMB-25
-55 to +125
Mil-STD-883
32 Ld LCC
32 Ld LCC
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8106.2
June 7, 2006

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Pinouts
X28C512, X28C513
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
NC 1
NC 2
32 VCC
31 WE
A15 3
30 NC
A12 4
29 A14
A7 5
28 A13
A6 6
27 A8
A5 7
26 A9
A4 8 X28C512 25 A11
A3 9
24 OE
A2 10
23 A10
A1 11
22 CE
A0 12
21 I/O5
I/O0 13
20 I/O4
I/O1 14
19 I/O3
I/O2 15
18 I/O2
VSS
16
17 I/O1
PGA
I/O0 I/O 2 I/O 3 I/O 5 I/O 6
15 17 19 21 22
A1
13
A0 I/O 1 VSS I/O 4 I/O 7 CE
14 16 18 20 23 24
A2
12
A3
11
A10 OE
25 26
A4 A5
10 9
A6 A7
87
Bottom
View
A11 A9
27 28
A8
29
A13
30
A12
6
A15
5
NC
2
VCC NC
36 34
NC
32
A14
31
NC NC NC WE NC
4 3 1 35 33
Pin Descriptions
Addresses (A0-A15)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512, X28C513.
Pin Names
SYMBOL
A0-A15
I/O0-I/O7
WE
CE
OE
VCC
VSS
NC
PLCC/LCC
30
A7 5 4 3 2 32 31 29 A14
A6 6
1 28 A13
A5 7
27 A8
A4
A3
8
9
X28C512
(Top View)
26
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20 21
I/O7
30
A6 5 4 3 2 32 31 29 A8
A5 6
1 28 A9
A4 7
27 A11
A3
A2
8
9
X28C513
(Top View)
26
25
NC
OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
14
15 16 17 18 19 20 21
I/O6
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
4 FN8106.2
June 7, 2006

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X28C512, X28C513
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C512, X28C513 support
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched internally
by the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C512, X28C513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to be
consecutively written to the X28C512, X28C513, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A7 through A15) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28C512, X28C513 provide the user two write
operation status bits. These can be used to optimize a
system write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling (I/O7)
The X28C512, X28C513 feature DATA polling as a method
to indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple bit
test operation to determine the status of the X28C512,
X28C513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx xxxx,
read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28C512, X28C513 also provide another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete, the toggling will
cease, and the device will be accessible for additional read
or write operations.
I/O DP TB 5 4 3 2 1 0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
5 FN8106.2
June 7, 2006