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®
Data Sheet
X40020, X40021
May 17, 2006
FN8112.1
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
VATdRjuIPs2t
programmable down to 0.9V
low voltage reset threshold voltages
using special programming sequence
MReosneittosrigtwnoalvvoalltiadgteosVoCrCd=et1eVct
power
fail
• Battery switch backup
FVaOuUlTt:d5emteActtioon50rmegAisftreorm VCC; 250µA from VBATT
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA battery current in backup mode
• 400kHz 2-wire interface
www.DataSheet4U.com 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• Monitor voltages: 5V to 1.6V
• Memory security
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
X40020, X40021
Standard VTRIP1 Level Standard VTRIP2, Level
4.6V (±1%)
2.9V(±1.7%)
4.6V (±1%)
2.6V (±2%)
2.9V(±1.7%)
1.6V (±3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40020 combines power-on reset control, watch-
dog timer, supply voltage supervision, and secondary
supervision, and manual reset, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
V2LMogoincitor
VOUT
+
- VTRIP2
Fault Detection
Register
Status
Register
Watchdog
and
Reset Logic
VOUT
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Power-on,
Manual Reset
Low Voltage
Reset
Generation
V2FAIL
WDO
MR
RESET
X40020
RESET
X40021
LOWLINE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X40020, 40021
Ordering Information
PART
NUMBER*
WITH RESET
PART
MARKING
PART
NUMBER*
WITH RESET
MONITORED VTRIP1
PART
VCC RANGE
MARKING SUPPLIES (mV)
VTRIP2
RANGE
TEMP.
(mV) RANGE (°C)
PACKAGE
PKG.
DWG. #
X40020S14-C X40020S C X40021S14-C X40021S C 1.6 to 3.6 2.9 ±50 1.6 ±50 0 to 70 14 Ld SOIC (150 mil) MDP0027
X40020S14I-C X40020S IC X40021S14I-C X40021S IC
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40020V14-C X4002 0VC X40021V14-C X4002 1VC
0 to 70 14 Ld TSSOP
(4.4mm)
M14.173
X40020V14I-C X4002 0VIC X40021V14I-C X4002 1VIC
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
X40020S14-B X40020S B X40021S14-B X40021S B 2.6 to 5.5 4.6 ±50 2.6 ±50 0 to 70 14 Ld SOIC (150 mil) MDP0027
X40020S14Z-B X40020S ZB X40021S14Z-B X40021S ZB
(Note)
(Note)
0 to 70 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020S14I-B X40020S IB X40021S14I-B X40021S IB
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40020S14IZ-B X40020S ZIB X40021S14IZ-B X40021S ZIB
(Note)
(Note)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020V14-B X4002 0VB X40021V14-B X4002 1VB
0 to 70 14 Ld TSSOP
(4.4mm)
M14.173
X40020V14Z-B X4002 0VZB X40021V14Z-B X4002 1VZB
(Note)
(Note)
0 to 70 14 Ld TSSOP
M14.173
(4.4mm) (Pb-free)
X40020V14I-B X4002 0VIB X40021V14I-B X4002 1VIB
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
X40020V14IZ-B X4002 0VZIB X40021V14IZ-B X4002 1VZIB
(Note)
(Note)
-40 to +85 14 Ld TSSOP
M14.173
(4.4mm) (Pb-free)
X40020S14-A X40020S A X40021S14-A X40021S A 2.9 to 5.5
2.9 ±50 0 to 70 14 Ld SOIC (150 mil) MDP0027
X40020S14Z-A X40020S ZA X40021S14Z-A X40021S ZA
(Note)
(Note)
0 to 70 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020S14I-A X40020S IA X40021S14I-A X40021S IA
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40020S14IZ-A X40020S ZIA X40021S14IZ-A X40021S ZIA
(Note)
(Note)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020V14-A X4002 0VA X40021V14-A X4002 1VA
0 to 70 14 Ld TSSOP
(4.4mm)
M14.173
X40020V14Z-A X4002 0VZA X40021V14Z-A X4002 1VZA
(Note)
(Note)
0 to 70 14 Ld TSSOP
M14.173
(4.4mm) (Pb-free)
X40020V14I-A X4002 0VIA X40021V14I-A X4002 1VIA
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
X40020V14IZ-A X4002 0VZIA X40021V14IZ-A X4002 1VZIA
(Note)
(Note)
-40 to +85 14 Ld TSSOP
M14.173
(4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2 FN8112.1
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X40020, 40021
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares VCC with VBATT input
and connects VOUT to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
PIN CONFIGURATION
X40020
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
50mA from VCC to 250µA from VBATT. The device only
switches to VBATT when VCC drops below the low VCC
voltage threshold and VBATT.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X40021
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a
not used.
second
power
supply
with
no
external
components.
Connect
V2MON
to
VSS
or
VCC
when
3
LOWLINE
Early
When
Low
VCC
VCC Detect. This
> VTRIP1, this pin
open drain output
is pulled high with
signal goes LOW when VCC < VTRIP1.
the use of an external pull up resistor.
4 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW
resistor.
until
the
pin
is
released
and
for
the
tPURST
thereafter.
It
has
an
internal
pull
up
6 RESET/ RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever
RESET
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
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X40020, 40021
PIN DESCRIPTION (Continued)
Pin Name
Function
7 VSS Ground
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10Mtypical)
11 VBATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
pmraiminataryinVthCeC
voltage.
contents
Tohf eSRVABAMTTanvdolatalsgoeptyopwicearsllythperoinvtiedrensalthloegsicutpop“lystvaoyltaawgaeknee.”cIef sthsearbyattotery
is
not
used, connect VBATT to ground.
12
VOUT
Output Voltage. (V)
VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1
then VOUT = VCC if VCC > VBATT + 0.03V
else VOUT = VBATT (ie if VCC < VBATT – 0.03V)
Nswoittech: oTvheerrevoisltahgyes.teArecsaispaacroitaunncdeVoBfA0T.T1µ±F0m.0u3sVt
point to avoid
be connected
oscillation at or near the
to VOUT to ensure stability.
13 BATT-ON Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when
VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
14 VCC Supply Voltage
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X40020, 40021
PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40020/21 activates a Power-
on Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40021) and RESET (X40020) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
System
Reset
X40020
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
tPURST or till the push-button is released and for tPURST
thereafter. A weak pull up resistor is connected to the
MR pin.
Low Voltage V1 Monitoring
During operation, the X40020/21 monitors the VCC
level and asserts RESET if supply voltage falls below
a preset minimum VTRIP1. The RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The V1FAIL signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP1 for tPURST.
Low Voltage V2 Monitoring
The X40020/21 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V2FAIL signal remains active until the VCC
drops below 1V (VCC falling). It also remains active until
V2MON returns and exceeds VTRIP2.
V2MON voltage monitor is powered by VOUT. If VCC
and VBATT go away, V2MON cannot be monitored.
Figure 2. Two Uses of Multiple Voltage Monitoring
X40020
VOUT
Unreg.
Supply
R
R
5V
Reg
VCC
RESET
V2MON
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
Unreg.
Supply
5V
Reg
3V
Reg
X40021
VOUT
VCC
RESET
V2MON
System
Reset
V2FAIL
Notice: No external components required to monitor two voltages.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. A standard
read or write sequence to any slave address byte
restarts the watchdog timer and prevents the WDO sig-
nal to go active. A minimum sequence to reset the
watchdog timer requires four microprocessor instructions
namely, a Start, Clock Low, Clock High and Stop. The
state of two nonvolatile control bits in the Status Register
determine the watchdog timer period. The microproces-
sor can change these watchdog bits by writing to the
X40020/21 control register (also refer to page 21).
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