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®
PRELIMINARY
Data Sheet
X40030, X40031, X40034, X40035
May 25, 2006
FN8114.1
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Standard reset threshold settings
see selection table on page 5.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three seperate voltages
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available in 14 Ld SOIC, TSSOP packages
www.DataSheet4U.com Monitor voltages: 5V to 0.9V
• Independent core voltage monitor
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communication equipment
—Routers, hubs, switches
—Disk arrays, network storage
BLOCK DIAGRAM
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
— Computers
—Network servers
DESCRIPTION
The X40030, X40031, X40034, X40035 combine
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision, and
manual reset, in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying voltage to VCC activates the power on reset cir-
cuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third voltage
monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be reprogrammed
to meet specific system level requirements or to fine-tune
the threshold for applications requiring higher precision.
V3MON
V2MON
V3LMoognicitor
+
-
V2LMogoincitor
VTRIP3
+
-
VCC or
V2MON*
VTRIP2
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
VCCLoMgoicnitor
+
VTRIP1
-
Watchdog
and
Reset Logic
Power on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40030/34
RESET
X40031/35
LOWLINE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X40030, X40031, X40034, X40035
Ordering Information
PART
PART NUMBER MARKING
PART NUMBER WITH RESET
MONITORED
VCC RANGE
VTRIP1
RANGE
VTRIP2
RANGE
VTRIP3
RANGE
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
X40034S14-A X40034S A
1.3 to 5.5 4.6V ±50mV 1.3V ±50mV 3.1V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15
X40034S14Z-A X40034S ZA
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14-B X40034S B
2.9V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15
X40034S14Z-B X40034S ZB
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14-C X40034S C
1.0 to 3.6
1.0V ±50mV
0 to 70 14 Ld SOIC (150 mil) M14.15
X40034S14I-A X40034S IA
1.3 to 5.5
1.3V ±50mV 3.1V ±50mV -40 to +85 14 Ld SOIC (150 mil) M14.15
X40034S14IZ-A X40034S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14I-B X40034S IB
2.9V ±50mV -40 to +85 14 Ld SOIC (150 mil) M14.15
X40034S14IZ-B X40034S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40034S14I-C X40034S IC
1.0 to 3.6
1.0V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40034V14-A X4003 4VA
1.3 to 5.5
1.3V ±50mV 3.1V ±50mV 0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40034V14Z-A X4003 4VZA
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14-B X4003 4VB
2.9V ±50mV 0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40034V14Z-B X4003 4VZB
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14-C X4003 4VC
1.0 to 3.6
1.0V ±50mV
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40034V14I-A X4003 4VIA
1.3 to 5.5
1.3V ±50mV 3.1V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40034V14IZ-A X4003 4VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14I-B X4003 4VIB
2.9V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40034V14IZ-B X4003 4VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40034V14I-C X4003 4VIC
1.0 to 3.6
1.0V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030S14-C X40030S C
1.7 to 3.6 2.9V ±50mV 2.2V ±50mV 1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil) M14.15
X40030S14I-C X40030S IC
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40030V14-C X4003 0VC
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40030V14I-C X4003 0VIC
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030S14-B X40030S B
1.7 to 5.5 4.4V ±50mV 2.6V ±50mV
0 to 70 14 Ld SOIC (150 mil) M14.15
X40030S14Z-B X40030S ZB
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030S14I-B X40030S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40030S14IZ-B X40030S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030V14-B X4003 0VB
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40030V14Z-B X4003 0VZB
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
2 FN8114.1
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X40030, X40031, X40034, X40035
Ordering Information (Continued)
PART
PART NUMBER MARKING
X40030V14I-B X4003 0VIB
MONITORED
VCC RANGE
VTRIP1
RANGE
1.7 to 5.5 4.4V ±50mV
VTRIP2
RANGE
2.6V ±50mV
VTRIP3
RANGE
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
1.7V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030V14IZ-B X4003 0VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40030S14-A X40030S A
4.6V ±50mV 2.9V ±50mV
0 to 70 14 Ld SOIC (150 mil) M14.15
X40030S14Z-A X40030S ZA
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030S14I-A X40030S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40030S14IZ-A X40030S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40030V14-A X4003 0VA
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40030V14Z-A X4003 0VZA
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40030V14I-A X4003 0VIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40030V14IZ-A X4003 0VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
PART NUMBER WITH RESET
X40035S14-A
X40035S14Z-A
(Note)
X40035S14-B
X40035S14Z-B
(Note)
X40035S A
X40035S ZA
X40035S B
X40035S ZB
1.3 to 5.5 4.6V ±50mV 1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to 70
0 to 70
0 to 70
0 to 70
14 Ld SOIC (150 mil) M14.15
14 Ld SOIC (150 mil) M14.15
(Pb-free)
14 Ld SOIC (150 mil) M14.15
14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14-C
X40035S14I-A
X40035S C
X40035S IA
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
0 to 70 14 Ld SOIC (150 mil) M14.15
1.3V ±50mV 3.1V ±50mV -40 to +85 14 Ld SOIC (150 mil) M14.15
X40035S14IZ-A X40035S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14I-B X40035S IB
2.9V ±50mV -40 to +85 14 Ld SOIC (150 mil) M14.15
X40035S14IZ-B X40035S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40035S14I-C X40035S IC
1.0 to 3.6
1.0V ±50mV
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40035V14-A
X40035V14-B
X40035V14Z-B
(Note)
X4003 5VA
X4003 5VB
X4003 5VZB
1.3 to 5.5
1.3V ±50mV 3.1V ±50mV
2.9V ±50mV
0 to 70
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14-C X4003 5VC
X40035V14Z-AT1 X4003 5VZA
(Note)
1.0 to 3.6
1.3 to 5.5
1.0V ±50mV
1.3V ±50mV 3.1V ±50mV
0 to 70
0 to 70
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP
Tape and Reel
(4.4mm) (Pb-free)
M14.173
X40035V14I-A X4003 5VIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40035V14IZ-A X4003 5VZIA
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14I-B X4003 5VIB
2.9V ±50mV -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40035V14IZ-B X4003 5VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40035V14I-C X4003 5VIC
1.0 to 3.6
1.0V ±50mV
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
3 FN8114.1
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X40030, X40031, X40034, X40035
Ordering Information (Continued)
PART
PART NUMBER MARKING
X40031S14-C X40031S C
MONITORED
VCC RANGE
VTRIP1
RANGE
1.7 to 3.6 2.9V ±50mV
VTRIP2
RANGE
2.2V ±50mV
VTRIP3
RANGE
TEMP.
RANGE (°C)
PACKAGE
1.7V ±50mV 0 to 70 14 Ld SOIC (150 mil)
PKG.
DWG. #
M14.15
X40031S14I-C X40031S IC
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40031V14-C
X40031V14I-C
X40031S14-B
X4003 1VC
X4003 1VIC
X40031S B
1.7 to 5.5 4.4V ±50mV 2.6V ±50mV
0 to 70 14 Ld TSSOP (4.4mm) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
0 to 70 14 Ld SOIC (150 mil) M14.15
X40031S14Z-B X40031S ZB
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031S14I-B X40031S IB
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40031S14IZ-B X40031S ZIB
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031V14-B X4003 1VB
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40031V14Z-B X4003 1VZB
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031V14I-B X4003 1VIB
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
X40031V14IZ-B X4003 1VZIB
(Note)
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031S14-A X40031S A
4.6V ±50mV 2.9V ±50mV
0 to 70 14 Ld SOIC (150 mil) M14.15
X40031S14Z-A X40031S ZA
(Note)
0 to 70 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031S14I-A X40031S IA
-40 to +85 14 Ld SOIC (150 mil) M14.15
X40031S14IZ-A X40031S ZIA
(Note)
-40 to +85 14 Ld SOIC (150 mil) M14.15
(Pb-free)
X40031V14-A X4003 1VA
0 to 70 14 Ld TSSOP (4.4mm) M14.173
X40031V14Z-A X4003 1VZA
(Note)
0 to 70 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
X40031V14I-A
X40031V14IZ-A
(Note)
X4003 1VIA
X4003 1VZIA
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4 FN8114.1
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X40030, X40031, X40034, X40035
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
Device
Expected System
Voltages
V(tVrip) 1
X40030, X40031
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
2.0-4.75*
4.55-4.65*
4.35-4.45*
2.95-3.05*
X40034, X40035
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
2.0-4.75*
4.55-4.65*
4.55-4.65*
4.55-4.65*
*Voltage monitor requires VCC to operate. Others are independent of VCC
PIN CONFIGURATION
X40030, X40034
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 WDO
12 V3FAIL
11 V3MON
10 WP
9 SCL
8 SDA
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
V(tVrip) 2
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
V(tVrip) 3
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
POR
(system)
RESET = X40030
RESET = X40031
RESET = X40030
RESET = X40031
X40031, X40035
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input
(X40034, X40035).
3
LOWLINE
Early
when
Low
VCC
VCC Detect.
> VTRIP1.
This
CMOS
output
signal
goes
LOW
when
VCC
<
VTRIP1
and
goes
high
4 NC No connect.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET/ RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW
RESET
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
5 FN8114.1
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