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®
Data Sheet
X4003, X4005
May 11, 2006
FN8113.1
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
www.DataSheet4U.com
BLOCK DIAGRAM
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
DESCRIPTION
These devices combine three popular functions,
Power-on Reset Control, Watchdog Timer, and Supply
Voltage Supervision. This combination lowers system
cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X4003, X4005
Ordering Information
PART NUMBER
PART NUMBER
RESET
PART
RESET
PART VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE PKG. DWG. #
X4003M8-4.5A ACH
X4005M8-4.5A ACQ
4.5 to 5.5 4.5 to 4.75
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-4.5A DAH
(Note)
X4005M8Z-4.5A DAP
(Note)
0 to 70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003M8I-4.5A ACI
X4005M8I-4.5A ACR
-40 to 85
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-4.5A DAD
(Note)
X4005M8IZ-4.5A DAM
(Note)
-40 to 85
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8-4.5A X4003 AL X4005S8-4.5A X4005 AL
0 to 70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z-4.5A X4003 ZAL X4005S8Z-4.5A X4005 ZAL
(Note)
(Note)
0 to 70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003S8I-4.5A X4003 AM X4005S8I-4.5A X4005 AM
-40 to 85
8 Ld SOIC
(150 mil)
MDP0027
X4003S8IZ-4.5A X4003 ZAM X4005S8IZ-4.5A X4005 ZAM
(Note)
(Note)
X4003M8
ACJ X4005M8 ACS
X4003M8Z (Note) DAE
X4005M8Z (Note) DER
X4003M8I
ACK
X4005M8I
ACT
X4003M8IZ (Note) DAA
X4005M8IZ
(Note)
DAJ
4.25 to 4.5
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8
X4003
X4005S8
X4005
X4003S8Z (Note) X4003 Z X4005S8Z (Note) X4005 Z
X4003S8I
X4003 I X4005S8I
X4005 I
X4003S8IZ (Note) X4003 ZI X4005S8IZ
(Note)
X4005 ZI
0 to 70
0 to 70
-40 to 85
-40 to 85
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8-2.7A ACL
X4005M8-2.7A ACU
2.7 to 5.5 2.85 to 3.0
X4003M8Z-2.7A DAG
(Note)
X4003M8I-2.7A ACM
X4005M8Z-2.7A DAO
(Note)
X4005M8I-2.7A ACV
X4003M8IZ-2.7A DAC
(Note)
X4005M8IZ-2.7A DAL
(Note)
X4003S8-2.7A X4003 AN X4005S8-2.7A X4005 AN
X4003S8Z-2.7A
(Note)
X4003S8I-2.7A
X4003 ZAN X4005S8Z-2.7A X4005 ZAN
(Note)
X4003 AP X4005S8I-2.7A X4005 AP
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
2 FN8113.1
May 11, 2006

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X4003, X4005
Ordering Information (Continued)
PART NUMBER
PART NUMBER
RESET
PART
RESET
PART VCC RANGE VTRIP RANGE TEMP. RANGE
(ACTIVE LOW) MARKING (ACTIVE HIGH) MARKING
(V)
(V)
(°C)
PACKAGE PKG. DWG. #
X4003S8IZ-2.7A X4003 ZAP X4005S8IZ-2.7A X4005 ZAP 2.7 to 5.5
(Note)
(Note)
2.85 to 3.0
-40 to 85
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8-2.7
ACN
X4005M8-2.7 ACW
2.55 to 2.7
0 to 70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-2.7
(Note)
DAF
X4005M8Z-2.7 DAN
(Note)
0 to 70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003M8I-2.7 ACO
X4005M8I-2.7 ACX
-40 to 85
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-2.7 DAB
(Note)
X4005M8IZ-2.7 DAK
(Note)
-40 to 85
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8-2.7
X4003 F X4005S8-2.7 X4005 F
0 to 70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z-2.7
(Note)
X4003 ZF X4005S8Z-2.7 X4005 ZF
(Note)
0 to 70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003S8I-2.7 X4003 G X4005S8I-2.7 X4005 G
-40 to 85
8 Ld SOIC
(150 mil)
MDP0027
X4003S8IZ-2.7 X4003 ZG X4005S8IZ-2.7 X4005 ZG
(Note)
(Note)
-40 to 85
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8113.1
May 11, 2006

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PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
NC
NC
RESET
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
X4003, X4005
PIN DESCRIPTION
Pin
(SOIC/DIP)
1
2
3
Pin
TSSOP
3
4
5
46
57
68
71
82
Pin
(MSOP)
2
3
4
5
6
1
Name
NC
NC
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
No internal connections
No internal connections
Reset Output. RESET/RESET is an active LOW/HIGH, open
drain output which goes active whenever VCC falls below the min-
imum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA re-
mains either HIGH or LOW longer than the selectable Watchdog
time out period. A falling edge of SDA, while SCL also toggles from
HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET/RESET goes active on power-
up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. This pin re-
quires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while
SCL also toggles from HIGH to LOW follow by a stop condition re-
sets the watchdog timer. The absence of this procedure within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The serial clock controls the serial bus timing for
data input and output.
Write Protect. WP HIGH prevents changes to the watchdog
timer setting.
Supply voltage
4 FN8113.1
May 11, 2006

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X4003, X4005
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4003/X4005 activates a
power-on reset circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to
stabilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When VCC exceeds the device VTRIP threshold value for
200ms (nominal) the circuit releases RESET/RESET,
allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
Set VTRIP Level Sequence (VCC = desired VTRIP value)
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL also toggles from HIGH
to LOW (this is a start bit) followed by a stop condition
prior to the expiration of the watchdog time out period
to prevent a RESET/RESET signal. The state of two
nonvolatile control bits in the control register deter-
mine the watchdog timer period. The microprocessor
can change these watchdog bits, or they may be
“locked” by tying the WP pin HIGH.
Figure 1. Watchdog Restart
.6µs
SCL
.6µs
SDA
Start
Condition
Restart
Stop
Condition
WP
SCL
VP = 15-18V
0 1 2 34 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SDA
A0h
01h
VCC THRESHOLD RESET PROCEDURE
The X4003/X4005 is shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard VTRIP is not
exactly right, or if higher precision is needed in the
VTRIP value, the X4003/X4005 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
00h
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher
voltage value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
5 FN8113.1
May 11, 2006