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®
PRELIMINARY
Data Sheet
X40420, X40421
4kbit EEPROM
March 28, 2005
FN8117.0
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 Programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery Switch Backup
• VOUT: 5mA to 50mA from VCC; or 250µA from
VBATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• •Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• VOUT 5mA to 50mA
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
X40420/21
Standard VTRIP1 Level Standard VTRIP2 Level
4.6V (+/-1%)
2.9V(+/-1.7%)
4.6V (+/-1%)
2.6V (+/-2%)
2.9V(+/-1.7%)
1.6V (+/-3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock
protect serial EEPROM in one package. This combi-
nation lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
V2 Monitor
Logic
VOUT
+
VTRIP2
-
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Watchdog
and
Reset Logic
VOUT
Power-on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X40420, X40421
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares VCC with VBATT input
and connects VOUT to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40420/21 can drive
50mA from VCC to 250µA from VBATT. The device only
switches to VBATT when VCC drops below the low VCC
voltage threshold and VBATT.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Example Application
Unreg.
Supply
5V
REG
BATT-ON
VCC
VBATT VOUT
+
X40420/21
V2MON
V2FAIL
VDO
RESET
MR
SCL SDA
Enable
SRAM
Addr
Manual
Reset
Addr
uC
NMI
IRQ
VCC
RESET
I2C
PIN CONFIGURATION
X40420
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
X40421
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used.
3 LOWLINE Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1.
When VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor.
4 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain
HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up resistor.
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X40420, X40421
PIN DESCRIPTION (Continued)
Pin Name
Function
6 RESET/ RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever
RESET
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
7 VSS Ground
8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10Mtypical)
11 VBATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not
used, connect VBATT to ground.
12
VOUT
Output Voltage. (V)
VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1
then VOUT = VCC if VCC > VBATT + 0.03V
else VOUT = VBATT (ie if VCC < VBATT - 0.03V)
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to VOUT to ensure stability.
13 BATT-ON Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when
VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
14 VCC Supply Voltage
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X40420, X40421
PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40420/21 activates a Power-
on Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40421) and RESET (X40420) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
System
Reset
X40420/21
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
tPURST or till the push-button is released and for tPURST
thereafter. A weak pull up resistor is connected to the
MR pin.
Low Voltage V1 Monitoring
During operation, the X40420/21 monitors the VCC
level and asserts RESET if supply voltage falls below
a preset minimum VTRIP1. The RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The V1FAIL signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP1 for tPURST.
Low Voltage V2 Monitoring
The X40420/21 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V2FAIL signal remains active until the VCC
drops below 1V (VCC falling). It also remains active until
V2MON returns and exceeds VTRIP2.
V2MON voltage monitor is powered by VOUT. If VCC
and VBATT go away, V2MON cannot be monitored.
Figure 2. Two Uses of Multiple Voltage Monitoring
X40420
VOUT
Unreg.
Supply
R
R
5V VCC
Reg RESET
V2MON
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
VOUT
Unreg.
Supply
X40421
5V
Reg
VCC
RESET
3V
Reg
V2MON
System
Reset
V2FAIL
Notice: No external components required to monitor two voltages.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal to go active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40420/21 control register.
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X40420, X40421
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
VCC/V2MON
WDO
VP
SCL 0
70
70
7
SDA
A0h
Figure 4. Watchdog Restart
.6µs
SCL
1.3µs
SDA
Start
WDT Reset Stop
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40420/21 is shipped with standard V1 and V2
threshold (VTRIP1, VTRIP2) voltages. These values will not
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in
the threshold value, the X40420 trip points may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.
Setting a VTRIPx Voltage (x = 1, 2)
There are two procedures used to set the threshold volt-
ages (VTRIPx), depending if the threshold voltage to be
stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x = 1, 2)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the
corresponding input pin (Vcc(V1MON) or V2MON).
Then, a program-ming voltage (Vp) must be applied to
the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for VTRIP1, and 09h for
VTRIP2, and a 00h Data Byte in order to program VTRIPx.
00h tWC
The STOP bit following a valid write operation initiates
the programming sequence. Pin WDO must then be
brought LOW to complete the operation.
To check if the VTRIPX has been set, set VXMON to a
value slightly greater than VTRIPX (that was previously
set). Slowly ramp down VXMON and observe when the
corresponding outputs (LOWLINE and V2FAIL) switch.
The voltage at which this occurs is the VTRIPX (actual).
CASE A
Now if the desired VTRIPX is greater than the VTRIPX
(actual), then add the difference between VTRIPX
(desired) - VTRIPX (actual) to the original VTRIPX desired.
This is your new VTRIPX that should be applied to
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
Now if the VTRIPX (actual), is higher than the VTRIPX
(desired), perform the reset sequence as described in
the next section. The new VTRIPX voltage to be applied
to VXMON will now be: VTRIPX (desired) - (VTRIPX
(actual) - VTRIPX (desired)).
Note: 1. This operation does not corrupt the memory
array.
2. Set VCC = 5V, when VTRIP2 is being pro-
grammed
Setting a Lower VTRIPx Voltage (x = 1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
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