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X40430, X40431, X40434, X40435
® 4Kbit EEPROM
Data Sheet
July 29, 2005
FN8251.0
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Monitoring voltages: 5V to 9V
• Independent core voltage monitor
• Triple voltage detection and reset assertion
—Standard reset threshold settings. See selec-
tion table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three separate voltages
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• Memory security
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lockprotect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil’s unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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BLOCK DIAGRAM
X40430, X40431, X40434, X40435
V3MON
V2MON
V3 Monitor
Logic
+
-
V2 Monitor
Logic
VTRIP3
VCC or
V2MON*
+
VTRIP2
-
SDA
Data
Register
WP Command
Decode Test
& Control
SCL Logic
Fault Detection
Register
Status
Register
EEPROM
Array
VCC
(V1MON)
*X40430, X40431=V2MON
X40434, X40435 =VCC
VCC Monitor
Logic
+
VTRIP1
-
Watchdog
and
Reset Logic
Power-on,
Manual Reset
Low Voltage
Reset
Generation
V3FAIL
V2FAIL
WDO
MR
RESET
X40430/34
RESET
X40431/35
LOWLINE
Device
Expected System
Voltages
Vtrip1(V)
X40430, X40431
-A 5V; 3V or 3.3V; 1.8V
-B 5V; 3V; 1.8V
-C 3.3V; 2.5V; 1.8V
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.95–3.05*
X40434, X40435
-A 5V; 3.3V; 1.5V
-B 5V; 3V or 3.3V; 1.5V
-C 5V; 3 or 3.3V; 1.2V
2.0–4.75*
4.55–4.65*
4.55–4.65*
4.55–4.65*
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
2.15–2.25
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
Vtrip3(V)
1.70–4.75
1.65–1.75
1.65–1.75
1.65–1.75
1.70–4.75
3.05–3.15
2.85–2.95
2.85–2.95
POR
(system)
RESET = X40430
RESET = X40431
RESET = X40434
RESET = X40435
PIN CONFIGURATION
X40430, X40434
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
X40431, X40435
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes
HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to VSS or VCC when not used. The
V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435).
3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when
VCC > VTRIP1.
4 NC No connect.
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X40430, X40431, X40434, X40435
PIN DESCRIPTION (Continued)
Pin Name
Function
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET/ RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
RESET ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for
tPURST thereafter.
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and for
tPURST thereafter.
7 VSS Ground
8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10Mtypical).
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to VSS or VCC when not used. The
V3MON comparator is supplied by the V3MON input.
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes
HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin.
13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
14 VCC Supply Voltage
PRINCIPLES OF OPERATION
Figure 1. Connecting a Manual Reset Push-Button
Power-on Reset
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.
System
Reset
X40430, X40434
VCC
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-
button is released and for tPURST thereafter.
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X40430, X40431, X40434, X40435
Low Voltage VCC (V1 Monitoring)
During operation, the X40430, X40431, X40434,
X40435 monitors the VCC level and asserts
RESET/RESET if supply voltage falls below a preset
minimum VTRIP1. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1
for tPURST.
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40430 and X40431 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
returns and exceeds VTRIP2. This voltage sense cir-
cuitry monitors the power supply connected to V2MON
pin. If VCC = 0, V2MON can still be monitored.
For the X40434 and X40435, the V2FAIL signal
remains active until VCC drops below 1V and remains
active until V2MON returns and exceeds VTRIP2. This
sense circuitry is powered by VCC. If VCC = 0, V2MON
cannot be monitored.
Low Voltage V3 Monitoring
The X40430, X40431, X40434, X40435 also monitors
a third voltage level and asserts V3FAIL if the voltage
falls below a preset minimum VTRIP3. The V3FAIL sig-
nal is either ORed with RESET to prevent the micro-
processor from operating in a power fail or brownout
condition or used to interrupt the microprocessor with
notification of an impending power failure. The V3FAIL
signal remains active until the V3MON drops below 1V
(V3MON falling). It also remains active until V3MON
returns and exceeds VTRIP3.
This voltage sense circuitry monitors the power supply
connected to V3MON pin. If VCC = 0, V3MON can still
be monitored.
Early Low VCC Detection (LOWLINE)
This CMOS output goes LOW earlier than
RESET/RESET whenever VCC falls below the VTRIP1
voltage and returns high when VCC exceeds the
VTRIP1 voltage. There is no power-up delay circuitry
(tPURST) on this pin.
Figure 2. Two Uses of Multiple Voltage Monitoring
X40431-A
6-10V
5V VCC RESET
1M 3.3V
390K
V2MON V2FAIL
V3MON
(1.7V) V3FAIL
VCC
System
Reset
Power
Fail
Interrupt
Unreg.
Supply
5V
Reg
3.0V
Reg
1.8V
Reg
X40431-B
VCC
VCC
RESET
V2MON
V2FAIL
V3MON
V3FAIL
System
Reset
Notice: No external components required to monitor three voltages.
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X40430, X40431, X40434, X40435
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
WDO
VP
SCL 0
70
70
7
SDA
A0h
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40430, X40431, X40434,
X40435 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Start
WDT Reset Stop
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430,
X40431, X40434, X40435 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.
5
00h tWC
Setting a VTRIPx Voltage (x = 1, 2, 3)
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage
to be stored is higher or lower than the present value.
For example, if the present VTRIPx is 2.9 V and the
new VTRIPx is 3.2 V, the new voltage can be stored
directly into the VTRIPx cell. If however, the new setting
is to be lower than the present setting, then it is neces-
sary to “reset” the VTRIPx voltage before setting the
new value.
Setting a Higher VTRIPx Voltage (x = 1, 2, 3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin Vcc(V1MON), V2MON or V3MON.
Then, a programming voltage (Vp) must be applied to the
WDO pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h, fol-
lowed by the Byte Address 01h for VTRIP1, 09h for
VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order
to program VTRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation. To
check if the VTRIPX has been set, set VXMON to a value
slightly greater than VTRIPX (that was previously set).
Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE, V2FAIL and V3FAIL)
switch. The voltage at which this occurs is the VTRIPX
(actual).
FN8251.0
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