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Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
www.DataSheet4U.com — 5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lockprotect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
V3MON
V2MON
V3 Monitor
Logic
+
VTRIP3
-
V2 Monitor
Logic
+
VTRIP2
-
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
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Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
+
VTRIP1
-
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Watchdog
and
Reset Logic
WDO
MR
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
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X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I2C bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
X40430
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
X40431
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC
when not used.
3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high
when VCC > VTRIP1.
4 NC No connect.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET/ RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever
RESET
VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power up. It will also stay active until manual reset is released
and for tPURST thereafter.
RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power up. It will also stay active until manual reset is released
and for tPURST thereafter.
7 VSS Ground
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X40430/X40431 – Preliminary Information
PIN DESCRIPTION (Continued)
Pin Name
Function
8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor.
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to VSS or VCC when
not used.
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and
goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin.
13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
14
VCC
Supply Voltage
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31 activates a Power
On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40431) and RESET (X40430) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40430
VCC
System
Reset
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for tPURST there-
after.
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X40430/X40431 – Preliminary Information
Low Voltage VCC (V1 Monitoring)
During operation, the X40430 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP1. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1
for tPURST.
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
VTRIP2 by 0.2V.
Low Voltage V3 Monitoring
The X40430 also monitors a third voltage level and
asserts V3FAIL if the voltage falls below a preset mini-
mum VTRIP3. The V3FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V3FAIL signal remains active
until the V3MON drops below 1V (V3MON falling). It
also remains active until V3MON returns and exceeds
VTRIP3 by 0.2V.
Early Low VCC Detection (LOWLINE)
This CMOS output goes LOW earlier than RESET/
RESET whenever VCC falls below the VTRIP1 voltage
and returns high when VCC exceeds the VTRIP1 volt-
age. There is no power up delay circuitry (tPURST) on
this pin.
Figure 2. Two Uses of Multiple Voltage Monitoring
Unreg.
Supply
R
R
X40430
5V VCC
Reg RESET
V2MON
V2FAIL
V2MON
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
Unreg.
Supply
5V
Reg
4V
Reg
3V
Reg
X40431
V2MON
VCC V3MON
VCC
RESET
V2MON
V2FAIL
System
Reset
V3MON
V3FAIL
Notice: No external components required to monitor three voltages.
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X40430/X40431 – Preliminary Information
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
WDO
SCL
0
70
VP
70
7
SDA
A0h
00h tWC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40430/
31 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Timer Start
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE
The X40430 is shipped with standard V1, V2 and V3
threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a VTRIPx Voltage (x=1, 2, 3)
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x=1, 2, 3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin (Vcc(V1MON), V2MON or V3MON).
The Vcc(V1MON), V2MON and V3MON must be tied
together during this sequence. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh for
VTRIP3, and a 00h Data Byte in order to program
VTRIPx. The STOP bit following a valid write operation
initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation
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Characteristics subject to change without notice. 5 of 24