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X5001
CPU Supervisor
Features
• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Adjust Low Vcc Reset Threshold Voltage using
special programming sequence
—Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile Watchdog Timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
• 2.7V to 5.5V Operation
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Watchdog Change Latch
• High Reliability
www.DataSheet4U.com Available Packages
—8-Lead TSSOP
—8-Lead SOIC
—8 Pin PDIP
Block Diagram
DESCRIPTION
This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
VTRIP thresholds are available, however, Xicor’s unique
circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The device utilizes Xicor’s proprietary Direct WriteTM cell
for the Watchdog TImer control bits and the VTRIP stor-
age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
SI
SO
SCK
CS/WDI
VCC
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
WATCHDOG
TRANSITION
DETECTOR
VTRIP
+
-
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
7078 1.1 8/9/99 CM
1
WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE
POWER ON/
LOW VOLTAGE
RESET
GENERATION
RESET
Characteristics subject to change without notice
7036 FRM 01

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X5001
PIN DESCRIPTION
PIN PIN
(SOIC/PDIP) TSSOP
Name
1 1 CS/WDI
2 2 SO
5 8 SI
6 9 SCK
3 6 VPE
4 7 VSS
8 14 VCC
7 13 RESET
3-5,10-12
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog
bits present on the SI pin. The falling edge of SCK changes the data output on
the SO pin.
VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last
valid programmed level. To readjust the VTRIP level, requires that the VPE pin
be pulled to a high voltage (15-18V).
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active
whenever Vcc falls below the minimum Vcc sense level. It will remain active un-
til Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active
if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW
longer than the selectable Watchdog time-out period. A falling edge of CS/WDI
will reset the Watchdog Timer. RESET goes active on power up at 1V and re-
mains active for 200ms after the power supply stabilizes.
No internal connections
Figure 1. PIN CONFIGURATION
RESET
VCC
CS/WDI
SO
8 Lead TSSOP
18
27
36
45
SCK
SI
V SS
VPE
8 Lead SOIC/PDIP
CS/WDI
SO
VPE
VSS
1
2
3
4
8 VCC
7 RESET
6 SCK
5 SI
2

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X5001
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5001 activates a Power On
Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the sys-
tem microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator. When
Vcc exceeds the device VTRIP value for 200ms (nominal)
the circuit releases RESET, allowing the processor to
begin executing code.
Low voltage monitoring
During operation, the X5001 monitors the VCC level and
asserts RESET if supply voltage falls below a preset mini-
mum VTRIP. The RESET signal prevents the microproces-
sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
exceeds VTRIP for 200ms.
watchdog timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Watchdog Register determine the watchdog timer period.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the Vcc pin and tie the WPE pin to the
programming voltage VP. Then a VTRIP programming
command sequence is sent to the device over the SPI
interface. This VTRIP programming sequence consists of
pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
CS HIGH. This initiates the VTRIP programming
sequence. VP is brought LOW to end the operation.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” volt-
age level. For example, if the current VTRIP is 4.4V and
the new VTRIP must be 4.0V, then the VTRIP must be
reset. When VTRIP is reset, the new VTRIP is something
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
To reset the VTRIP voltage, apply greater than 3V to the
Vcc pin and tie the WPE pin to the programming voltage
Vp. Then a VTRIP command sequence is sent to the
device over the SPI interface. This VTRIP programming
sequence consists of pulling CS LOW, then clocking in
data 03h, 00h and 01h. This is followed by bringing CS
HIGH then LOW and clocking in data 02h, 00h, and 03h
(in order) and bringing CS HIGH. This initiates the VTRIP
programming sequence. VP is brought LOW to end the
operation.
Vcc Threshold Reset Procedure
The X5001 is shipped with a standard Vcc threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the X5001
threshold may be adjusted. The procedure is described
below, and requires the application of a high voltage con-
trol signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher volt-
age value. For example, if the current VTRIP is 4.4V and
the new VTRIP is 4.6V, this procedure will directly make
the change. If the new setting is to be lower than the cur-
rent setting, then it is necessary to reset the trip point
before setting the new value.
3

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X5001
Figure 2. Sample VTRIP Reset Circuit
VTRIP
Adj.
VP
Adjust
Run
1
2
3 X5001
4
8
7
6
5
4.7K
RESET
uC
SCK
SI
SO
CS
Figure 3. Set VTRIP Level Sequence (Vcc=desired VTRIP value. )
VPE VPE = 15-18V
CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
SCK
SI
03h
16 BITS
0001h
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
16 BITS
02h 0001h
Figure 4. Reset VTRIP Level Sequence (Vcc > 3V. )
VPE VPE = 15-18V
CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
SCK
SI
03h
16 BITS
0001h
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
16 BITS
02h 0003h
4

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X5001
Figure 5. Vtrip Programming Sequence
New Vcc applied =
Old Vcc applied + Error
Vtrip Programming
Execute
Reset Vtrip
Sequence
Set Vcc = Vcc applied =
Desired Vtrip
Execute
Set Vtrip
Sequence
Apply 5V to Vcc
Decrement Vcc
(Vcc = Vcc - 50mV)
New Vcc applied =
Old Vcc applied - Error
Execute
Reset Vtrip
Sequence
NO
Error < 0
RESET pin
goes active?
YES
Measured Vtrip -
Desired Vtrip
Error > 0
Error = 0
DONE
5