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®
Data Sheet
CPU Supervisor
FEATURES
• 200ms power-on reset delay
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Selectable nonvolatile watchdog timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
• 2.7V to 5.5V operation
• SPI mode 0 interface
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Watchdog change latch
• High reliability
• Available packages
— 8 Ld TSSOPwww.DataSheet4U.com
—8 Ld SOIC
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
Watchdog
Transition
Detector
VCC
VTRIP
+
-
May 30, 2006
X5001
FN8125.1
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low VCC detection circuitry. When
VCC falls below the minimum VCC trip point, the system
is reset. RESET is asserted until VCC returns to proper
operating levels and stabilizes. Five industry standard
VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil’s proprietary Direct Write
cell for the watchdog timer control bits and the VTRIP
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
Watchdog
Timer
Reset &
Watchdog
Timebase
Power-on/
Low Voltage
REset
Generation
RESET
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X5001
Ordering Information
PART NUMBER PART MARKING VCC RANGE (V)
X5001P-2.7
X5001P F
2.7 to 5.5
X5001PZ-2.7 (Note) X5001P ZF
VTRIP RANGE
2.55 to 2.7
X5001PI-2.7
X5001P G
X5001PIZ-2.7 (Note) X5001P ZG
X5001S8-2.7
X5001S8Z-2.7
(Note)
X5001S8I-2.7
X5001S8IZ-2.7
(Note)
X5001V8-2.7
X5001V8Z-2.7
(Note)
X5001V8I-2.7
X5001V8IZ-2.7
(Note)
X5001P-2.7A
X5001PZ-2.7A
(Note)
X5001PI-2.7A
X5001PIZ-2.7A
(Note)
X5001S8-2.7A
X5001S8Z-2.7A
(Note)
X5001S8I-2.7A
X5001S8IZ-2.7A
(Note)
X5001V8-2.7A
X5001V8Z-2.7A
(Note)
X5001V8I-2.7A
X5001V8IZ-2.7A
(Note)
X5001PI
X5001PIZ (Note)
X5001 F
X5001 ZF
X5001 G
X5001 ZG
501 F
5001 FZ
501 G
5001 GZ
X5001P AN
X5001P ZAN
X5001P AP
X5001P ZAP
X5001 AN
X5001 ZAN
X5001 AP
X5001 ZAP
501 AN
5001 ANZ
501 AP
5001 APZ
X5001P I
X5001P ZI
2.85 to 3.0
4.5 to 5.5
4.25 to 4.5
X5001S8
X5001S8Z (Note)
X5001
X5001 Z
X5001S8I
X5001S8IZ (Note)
X5001 I
X5001 ZI
TEMP. RANGE
(°C)
PACKAGE
0 to 70
8 Ld PDIP
0 to 70
8 Ld PDIP (300 mil)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
0 to 70
8 Ld TSSOP (4.4mm)
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85 8 Ld TSSOP (4.4mm)
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
0 to 70
8 Ld PDIP
0 to 70
8 Ld PDIP (300 mil)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
0 to 70
8 Ld TSSOP (4.4mm)
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85 8 Ld TSSOP (4.4mm)
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
-40 to 85
8 Ld PDIP
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
0 to 70
8 Ld SOIC (150 mil)
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
-40 to 85
8 Ld SOIC (150 mil)
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
2
PKG. DWG. #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
FN8125.1
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X5001
Ordering Information (Continued)
PART NUMBER
X5001V8
PART MARKING VCC RANGE (V)
501 4.5 to 5.5
VTRIP RANGE
4.25 to 4.5
TEMP. RANGE
(°C)
PACKAGE
0 to 70
8 Ld TSSOP (4.4mm)
PKG. DWG. #
M8.173
X5001V8Z (Note) 5001 Z
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
M8.173
X5001V8I
501 I
-40 to 85 8 Ld TSSOP (4.4mm)
M8.173
X5001V8IZ (Note) 5001 IZ
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
M8.173
X5001PI-4.5A
X5001P AM
4.5 to 5.5
4.5 to 4.75
-40 to 85
8 Ld PDIP
MDP0031
X5001PIZ-4.5A
(Note)
X5001P ZAM
-40 to 85
8 Ld PDIP (300 mil)
(Pb-free)
MDP0031
X5001S8-4.5A
X5001 AL
0 to 70
8 Ld SOIC (150 mil)
MDP0027
X5001S8Z-4.5A
(Note)
X5001 ZAL
0 to 70
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
X5001S8I-4.5A
X5001 AM
-40 to 85
8 Ld SOIC (150 mil)
MDP0027
X5001S8IZ-4.5A
(Note)
X5001 ZAM
-40 to 85
8 Ld SOIC (150 mil)
(Pb-free)
MDP0027
X5001V8-4.5A
501 AL
0 to 70
8 Ld TSSOP (4.4mm)
M8.173
X5001V8Z-4.5A
(Note)
5001 ALZ
0 to 70
8 Ld TSSOP (4.4mm)
(Pb-free)
M8.173
X5001V8I-4.5A
501 AM
-40 to 85 8 Ld TSSOP (4.4mm)
M8.173
X5001V8IZ-4.5A
(Note)
5001 AMZ
-40 to 85
8 Ld TSSOP (4.4mm)
(Pb-free)
M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8125.1
May 30, 2006

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PIN CONFIGURATION
RESET
VCC
CS/WDI
SO
8 Ld TSSOP
1
2 X5001
3
4
8
7
6
5
X5001
SCK
SI
VSS
VPE
CS/WDI
SO
VPE
VSS
8 Ld SOIC/PDIP
18
2 X5001 7
36
45
VCC
RESET
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
Pin
TSSOP
1
22
58
69
36
47
8 14
7 13
3-5,10-12
Name
CS/WDI
SO
SI
SCK
VPE
VSS
VCC
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
VvaTlRidIPpProrgorgarmammeEdnleavbelel..TWohreeandVjuPsEt
tisheLOVTWR,IPthleevVelT,RreIPqpuoirienst
is fixed
that the
at the last
VPE pin be
pulled to a high voltage (15-18V).
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active un-
til VCC rises above the minimum VCC sense level for 200ms. RESET goes active
if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long-
er than the selectable watchdog time out period. A falling edge of CS/WDI will
reset the watchdog timer. RESET goes active on power-up at 1V and remains
active for 200ms after the power supply stabilizes.
No internal connections
4 FN8125.1
May 30, 2006

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X5001
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X5001 activates a power-
on reset circuit. This circuit goes active at 1V and pulls
the RESET/RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
oscillator. When VCC exceeds the device VTRIP value
for 200ms (nominal) the circuit releases RESET,
allowing the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5001 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microproces-
sor must toggle the CS/WDI pin periodically to prevent
a RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watch-
dog time out period. The state of two nonvolatile control
bits in the watchdog register determine the watchdog
timer period.
Vcc Threshold Reset Procedure
The X5001 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X5001 threshold may be adjusted. The procedure is
described in the following sections, and requires the
application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher
voltage value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WPE pin to
the programming voltage VP. Then a VTRIP programming
command sequence is sent to the device over the SPI
interface. This VTRIP programming sequence consists of
pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
CS HIGH. This initiates the VTRIP programming
sequence. VP is brought LOW to end the operation.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the VTRIP voltage, apply greater than 3V to
the VCC pin and tie the WPE pin to the programming
voltage VP. Then a VTRIP command sequence is sent
to the device over the SPI interface. This VTRIP pro-
gramming sequence consists of pulling CS LOW, then
clocking in data 03h, 00h and 01h. This is followed by
bringing CS HIGH then LOW and clocking in data 02h,
00h, and 03h (in order) and bringing CS HIGH. This
initiates the VTRIP programming sequence. VP is
brought LOW to end the operation.
5 FN8125.1
May 30, 2006