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®
Data Sheet
March 9, 2006
ISL6421A
FN9167.3
Single Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-top Box Designs
The ISL6421A is a highly integrated solution for providing
power and control signals from advanced satellite set-top
box (STB) modules to the low noise block (LNB). The
internal architecture of this device contains a current-mode
boost PWM and a low-noise linear regulator, along with the
circuitry required for I2C device interfacing and for providing
DiSEqC™ standard control signals to the LNB.
A regulated output voltage is available at the output terminal
(VOUT) to support the operation of the antenna port in
advanced satellite STB applications. The regulated output
may be set to either 13V or 18V by use of the voltage select
command bit (VSEL) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
voltage may be increased by 1V with the line length
compensation bit (LLC) feature. The device can be put into a
standby mode by means of the enable bit (EN), this disables
the PWM and Linear regulator combination and helps
conserve power.
The input to the linear regulator is derived from the current
mode boost converter, such that the required voltage is the
sum of the output voltage and the linear regulator drop (1.0V
typical). This ensures that the power dissipation is minimized
and maintains a constant voltage drop across the linear pass
element, while permitting an adequate voltage range for tone
injection.
The device is capable of providing 450mA (typical). The
overcurrent limit is either digitally or resistor programmable.
Pinout
ISL6421A (QFN) TOP VIEW
32 31 30 29 28 27 26 25
PGND 1
24 CPSWOUT
NC 2
23 NC
SGND 3
22 NC
SEL18V 4
21 NC
NC 5
20 AGND
BYPASS 6
19 VOUT
PGND 7
18 DSQIN
GATE 8
17 TCAP
9 10 11 12 13 14 15 16
Features
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWM with >92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
- Vsw tracks Vout ensures low dissipation
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Fully Functional 3.3V, 5V Operation up to 400kHz
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC™ (EUTELSAT) Encoding
- External Modulation input DSQIN
• Internal Over Temperature Protection and Diagnostics
• Internal Overload and Over Temperature Flags
(Visible on I2C)
• Output Back-Bias Protection to 24V
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• External Pins to Select 13V/18V Options
• Pb-Free Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
Ordering Information
PART
NUMBER*
PART
MARKING
TEMP.
RANGE
(°C)
PKG.
PACKAGE DWG. #
ISL6421AER ISL6421AER -20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6421AERZ ISL6421AERZ -20 to 85 32 Ld 5x5 QFN L32.5x5
(Note)
(Pb-free)
*Add -T for tape and reel package.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
COUNTER
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF
DCL
SEL18V
GATE
PGND
PWM
LOGIC
Q
S
CLK
OC
CS
COMP
CS ILIM
AMP
SLOPE
COMPENSATION
FB
VREF
VSW
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ
ISEL
EN
ENT
OLF
I2C
INTERFACE
SDA
ADDR
SCL
OTF
LLC VSEL
DCL
CLK
OSC.
220kHz
BGV
÷ 10 AND
WAVE SHAPING
TONE
INJ
CKT
22kHz
TONE
VOUT
VCC
SGND
ON CHIP
LINEAR
UVLO
POR
SOFT-START
INT 5V
SOFT-START
EN
+-
OTF
THERMAL
SHUTDOWN
CHARGE PUMP
CPSWOUT
SDA
ADDR
SCL
ENT
DSQIN
CPVOUT
CPSWIN

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Typical Application Schematic
NOTE: SGND and PGND to be shorted as close to U1 at layout

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ISL6421A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range (SDA, SCL, ENT) . . . . . . . . -0.5V to 7V
Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited
Thermal Information
Thermal Resistance (Notes 1, 2)
θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
35
6
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
NOTE: The device junction temperature should be kept below
150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +150°C typically.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VCC
ENT
=
=
12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA
L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software
= 25°C. EN
description
= H, LLC = L,
section for I2C
access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN = L
-
1.5 3.0
mA
Supply Current
UNDERVOLTAGE LOCKOUT
IIN EN = LLC = VSEL = ENT = H, No Load
-
4.0 8.0
mA
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 3)
(Note 5)
- 1024 - Cycles
OUTPUT VOLTAGE
Output Voltage (Note 4)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
Dynamic Overload Protection Off Time
Dynamic Overload Protection On Time
Output Backward Current
22kHz TONE
VOUT
VOUT
VOUT
VOOU
DVOUT
DVOUT
IMAX
TOFF
TON
IOBK
VSEL = L, LLC = L
VSEL = L, LLC = H
VSEL = H, LLC = L
VSEL = H, LLC = H
VIN = 8V to 14V; VOUT = 13V
VIN = 8V to 14V; VOUT = 18V
IO = 12mA to 450mA
DCL = L
DCL = L, Output Shorted (Note 5)
EN = 0; VOBK = 24V
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
- 4.0 40.0
- 4.0 60.0
- 50 80
500 - 625
- 900 -
- 20 -
- 2.0 3.0
V
V
V
V
mV
mV
mV
mA
ms
ms
mA
Tone Frequency
Tone Amplitude
Tone Duty Cycle
Tone Rise or Fall Time
ftone
Vtone
dctone
Tr, Tf
ENT = H
ENT = H
ENT = H
ENT = H
20.0 22.0 24.0
500 680 900
40 50 60
5 8 14
kHz
mV
%
µs
4 FN9167.3
March 9, 2006

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ISL6421A
Electrical Specifications
VCC
ENT
=
=
12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA
L, DCL = L, DSQIN = L, Iout = 12mA, unless otherwise noted. See software
= 25°C. EN
description
= H, LLC = L,
section for I2C
access to the system. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
LINEAR REGULATOR
Drop-out Voltage
Iout = 450mA (Note 5)
- 1.2 -
V
DSQIN PIN
DSQIN pin logic Low
-
- 1.5V
V
DSQIN pin Logic HIGH
3.5 -
-
V
DSQIN pin Input Current
- 1 - µA
CURRENT SENSE
Input Bias Current
Overcurrent Threshold
IBIAS
Static current mode, DCL = H
- 700 -
325 400 500
nA
mV
ERROR AMPLIFIER
Open Loop Voltage Gain
Gain Bandwidth Product
PWM
AOL (Note 5)
GBP (Note 5)
70 88
-
dB
10 -
- MHz
Maximum Duty Cycle
90 93
-
%
Minimum Pulse Width
(Note 5)
- 20 -
ns
OSCILLATOR
Oscillator Frequency
THERMAL PROTECTION
fo Fixed at (10)(ftone)
200 220 240
kHz
Thermal Shutdown
Temperature Shutdown Threshold
(Note 5)
- 150 -
°C
Temperature Shutdown Hysteresis
(Note 5)
- 20 -
°C
NOTES:
3. Internal digital soft-start.
4. Voltage programming signals VSEL and LLC are implemented via the I2C bus.
IO1 = IO2 = 500mA.
5. Guaranteed by design.
Functional Pin Description
SYMBOL
SDA
SCL
Bidirectional data from/to I2C bus.
Clock from I2C bus.
FUNCTION
VSW
Input of the linear post-regulator.
PGND
Dedicated ground for the output gate driver of the PWM.
CS Current sense input; connect Rsc at this pin for desired overcurrent value for the PWM.
SGND
Small signal ground for the IC.
AGND
Analog ground for the IC.
TCAP
Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1µF or higher.
BYPASS
Bypass capacitor for internal 5V.
DSQIN
When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for the
LNB.
5 FN9167.3
March 9, 2006