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Data Sheet
November 10, 2015
ISL6596
FN9240.2
Synchronous Rectified MOSFET Driver
The ISL6596 is a high frequency, MOSFET driver optimized
to drive two N-Channel power MOSFETs in a synchronous
buck converter topology. This driver combined with Intersil’s
Multi-Phase Buck PWM controllers forms a complete single-
stage core-voltage regulator solution with high efficiency
performance at high switching frequency for advanced
microprocessors.
The IC is biased by a single low voltage supply (5V),
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications.
Each driver is capable of driving a 3nF load with less than
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode,
reducing implementation cost, complexity, and allowing the
use of higher performance, cost effective N-Channel
MOSFETs. Adaptive shoot-through protection is integrated
to prevent both MOSFETs from conducting simultaneously.
The ISL6596 features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
The ISL6596 also features an input that recognizes a
high-impedance state, working together with Intersil
multi-phase 3.3V or 5V PWM controllers to prevent negative
transients on the controlled output voltage when operation is
suspended. This feature eliminates the need for the schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
Applications
• Core Voltage Supplies for Intel® and AMD®
Microprocessors
• High Frequency Low Profile High Efficiency DC/DC
Converters
• High Current Low Voltage DC/DC Converters
• Synchronous Rectification for Isolated Power Supplies
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• 0.4On-Resistance and 4A Sink Current Capability
• Supports High Switching Frequency
• Fast Output Rise and Fall Time
• Low Tri-State Hold-Off Time (20ns)
• Support 3.3V and 5V PWM Input
• Low Quiescent Supply Current
• Power-On Reset
• Expandable Bottom Copper Pad for Heat Spreading
• Dual Flat No-Lead (DFN) Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
TEMP
PART RANGE
MARKING (°C)
PACKAGE
PKG.
DWG. #
ISL6596CBZ* 6596 CBZ
(No longer
available,
recommended
replacement:
ISL6596CRZ)
0 to +70 8 Ld SOIC
M8.15
ISL6596CRZ* 596Z
0 to +70 10 Ld 3x3 DFN L10.3x3C
ISL6596IBZ* 6596 IBZ
(No longer
available,
recommended
replacement:
ISL6596IRZ)
-40 to +85 8 Ld SOIC
M8.15
ISL6596IRZ* 96IZ
-40 to +85 10 Ld 3x3 DFN L10.3x3C
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright © Intersil Americas LLC. 2005, 2010, 2015. All Rights Reserved
Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.

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Pinout
ISL6596
(8 LD SOIC)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
NGONLDONG4ER
AVAILABLE
OR
SUP87PORPVECHDTARSLE
6 VCC
5 LGATE
ISL6596
ISL6596
(10 LD DFN)
TOP VIEW
UGATE 1
BOOT 2
N/C 3
PWM 4
GND 5
10 PHASE
9 VCTRL
8 N/C
7 VCC
6 LGATE
Block Diagram
ISL6596
VCC
VCTRL
PWM
7k
CONTROL
LOGIC
7k
SHOOT-
THROUGH
PROTECTION
VCC
VCTRL = CONTROLLER VCC
BOOT
UGATE
PHASE
LGATE
GND
2 FN9240.2
November 10, 2015

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ISL6596
Typical Application - Multi-Phase Converter Using ISL6596 Gate Drivers
+3.3V
PGOOD
VID
(OPTIONAL)
+3.3V
FB COMP
VCC
VSEN
PWM1
PWM2
PWM
CONTROLLER
(ISL69XX)
ISEN1
ISEN2
FS/EN
GND
+5V
VCC
BOOT
VCTRL
PWM
UGATE
ISL6596
PHASE
LGATE
+5V
VCC
BOOT
VCTRL
PWM
UGATE
ISL6596
PHASE
LGATE
VIN
RUGPH
VIN
RUGPH
RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS
(SEE APPLICATION INFORMATION SECTION ON PAGE 8)
+VCORE
3 FN9240.2
November 10, 2015

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ISL6596
Absolute Maximum Ratings
Supply Voltage (VCC, VCTRL) . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
. . . . . . . . . GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
. . . . . . . . . . . VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
. . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance
JA (°C/W) JC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 110
N/A
DFN Package (Notes 2, 3) . . . . . . . . . . 48
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +100°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications These specifications apply for “Recommended Operating Conditions” on page 4, unless otherwise
noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 5) TYP (Note 5) UNITS
VCC SUPPLY CURRENT
Bias Supply Current
POR Rising
IVCC
PWM pin floating, VVCC = 5V
- 190 -
- 3.4 4.2
µA
POR Falling
2.2 3.0
-
Hysteresis
- 400 -
mV
VCTRL INPUT
Rising Threshold
- 2.75 2.90
V
Falling Threshold
2.4 2.65
-
V
PWM INPUT
Sinking Impedance
Source Impedance
Tri-State LowerThreshold
Tri-State Upper Threshold
Tri-State Shutdown Holdoff Time
SWITCHING TIME (See Figure 1 on page 6)
RPWM_SNK
RPWM_SRC
tTSSHD
VVCTRL = 3.3V (-110mV Hysteresis)
VVCTRL = 5V (-250mV Hysteresis)
VVCTRL = 3.3V (+110mV Hysteresis)
VVCTRL = 5V (+250mV Hysteresis)
tPDLU or tPDLL + Gate Falling Time
- 3.5 -
- 3.5 -
- 1.1 -
- 1.5 -
- 1.9 -
- 3.25 -
- 20 -
k
k
V
V
V
V
ns
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
tRU
tRL
tFU
tFL
tPDLU
tPDLL
tPDHU
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, Outputs Unloaded
VVCC = 5V, Outputs Unloaded
VVCC = 5V, Outputs Unloaded
- 8.0 -
- 8.0 -
- 8.0 -
- 4.0 -
- 20 -
- 15 -
- 19 -
ns
ns
ns
ns
ns
ns
ns
4 FN9240.2
November 10, 2015

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ISL6596
Electrical Specifications These specifications apply for “Recommended Operating Conditions” on page 4, unless otherwise
noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 5) TYP (Note 5) UNITS
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
tPDHL
tPTS
VVCC = 5V, Outputs Unloaded
VVCC = 5V, Outputs Unloaded
- 18 -
- 30 -
ns
ns
Upper Drive Source Resistance
RUG_SRC 250mA Source Current
- 1.0 2.5
Upper Drive Sink Resistance
RUG_SNK 250mA Sink Current
- 1.0 2.5
Lower Drive Source Resistance
RLG_SRC 250mA Source Current
- 1.0 2.5
Lower Drive Sink Resistance
RLG_SNK 250mA Sink Current
- 0.4 1.0
NOTES:
4. Limits established by characterization and are not production tested.
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5 FN9240.2
November 10, 2015