ISL6271A.pdf 데이터시트 (총 16 페이지) - 파일 다운로드 ISL6271A 데이타시트 다운로드

No Preview Available !

®
Data Sheet
October 8, 2004
ISL6271A
FN9171.1
Integrated XScale Regulator
The ISL6271A is a versatile power management IC (PMIC)
designed for the Xscale type of processors. The device
integrates three regulators, two fault indicators and an I2C
bus for communication with a host microprocessor. Two of
the three regulators function as low power, low drop out
regulators, designed to power SRAM and phase-lock loop
circuitry internal to the Xscale processor. The third regulator
uses a proprietary switch-mode topology to power the
processor core and facilitate Dynamic Voltage Management
(DVM), as defined by Intel.
Since power dissipation inside a microprocessor is
proportional to the square of the core voltage, Intel XScale
processors implement DVM as a means to more efficiently
utilize battery capacity. To support this power saving
architecture, the ISL6271A integrates an I2C bus for
communication with the host processor. The processor, acting
as the bus master, transmits a “voltage level” and “voltage
slew rate” to the ISL6271A appropriate to the processing
requirements; higher core voltages support higher operating
frequencies and code execution. The bus is fully compliant
with the Phillips® I2C protocol and supports both standard
and fast data transmission modes. Alternatively, the output of
the core regulator can be programmed in 50mV increments
from 0.85V to 1.6V using the input Voltage ID (VID) pins. All
three regulators share a common enable pin and are
protected against overcurrent, over temperature and
undervoltage conditions. When disabled via the enable pin,
the ISL6271A enters a low power state that can be used to
conserve battery life while maintaining the last programmed
VID code and slew rate. An integrated soft-start circuit
transitions the ISL6271A output voltages to their default
values at a rate determined by an external soft-start capacitor.
Pinout
ISL6271A (4x4 QFN) TOP VIEW
20 19 18 17 16
VCC 1
VIDEN 2
SCL/VID0 3
SDA/VID1 4
VID2 5
15 LVCC
14 VPLL
13 VSRAM
12 FB
11 VOUT
6 7 8 9 10
Features
• Three Voltage Regulators (1 Buck, 2 LDOs)
• High-Efficiency, fully-Integrated synchronous buck
regulator with DVM
• 800mA DC output current for the buck regulator
• Proprietary ‘Synthetic Ripple’ Control Topology
• Greater than 1MHz Switching Frequency
• Diode emulation for light load efficiency
• I2C Interface Module for DVM from 0.85V to 1.6V
• Optional fixed 4-bit VID-control in lieu of DVM
• Small Output Inductor and Capacitor
• Battery Fault signal
• Input Supply Voltage Range: 2.76V-5.5V
• 4x4 mm QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free Available (RoHS Compliant)
Applications
• PDA
• Cell Phone
• Tablet Devices
• Embedded Processors
Related Literature
• Technical Brief TB379 “Thermal Characterization of
Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages“
• Application Note AN1139 “Setup Instruction for the
ISL6271 Evaluation Kit”
Ordering Information
PART NUMBER*
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6271ACR
-25 to 85 20 Ld 4x4 QFN L20.4x4
ISL6271ACRZ (Note)
-25 to 85
20 Ld 4x4 QFN L20.4x4
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
Intel® is a registered trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.

No Preview Available !

Regulator Block Diagram
ISL6271A
LVCC
EN
PVCC
SCL (VID 0)
SDA (VID 1)
VID2
VID3
VIDEN
LDO1
LDO2
I2C
&
STATIC
VID
LOGIC
DAC
SWITCHING
REGULATOR
FIGURE 1. BULVERDE POWER CONTROLLER
VSRAM
(VCC_SRAM)
VPLL
(VCC_PLL)
VOUT
(VCC_VCORE)
Functional Block Diagram
SCL/VID0
SDA/VID1
VID2
VID3
EN
SOFT
CSS
FB
VIDEN
PGOOD BFLT#
BBAT
VCC 1.1V VSRAM 1.3V VPLL
I2C
OV
UV OT
POR
TEMP
MONITOR
LDO1 AND LDO2
OVERCURRENT
DETECT
DAC
VOUT VCC_CORE OV
MONITOR UV
+
- CMP
GATE
DRIVE
LOGIC
ERROR
AMP
+
-
C RP
RIPPLE
AMP
+
-
GATE
DRIVE
&
ZERO
CURRENT
DETECT
50
RC CC
RCOMP
RRP
GND
RING DAMPING CIRCUIT
VOUT
LVCC
PVCC
CIN
Lo
PHASE
PGND
1.8V TO 5.5V
2.6V TO 5.5V
VOUT
COUT
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
2 FN9171.1

No Preview Available !

ISL6271A
Absolute Maximum Ratings
(PVCC, VCC, LVCC) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
PHASE to PGND . . . . . . . . . . . . . . . . . . . . . .-0.3V to (PVCC +0.3V)
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All other pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .2kV
Thermal Information
Thermal Resistance. . . . . . . . . . . . . . . . . θJA (°C/W) θJC (°C/W)
4x4 QFN Package (Notes 1, 2) . . . .
45
7.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-25°C to 85°C
Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . 2.76 to 5.5V
Supply Voltage (LVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 - 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features (TB379).
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Operating
as shown
iCn oFnigduitrioen1s9, ,UTnylpeiscsalOAthpeprliwcaisteioNn oCteirdcu; iTt:AV=ou-2t 5=°C1.6toV,8I5O°UCT,
PVCC =
= 0mA
VCC
=
3.7V.
Component
values
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
CORE BUCK REGULATOR
Input Voltage Range
(After VCC reaches Rising VPOR)
Output Voltage Nominal Range
PVCC
VOUT
PVCC = VCC
Programmable in 50mV increments
2.76
0.85
5.5 V
1.60 V
Max. DC Output Current
Icore
(Note 3)
800 mA
Current Limit (DC plus Ripple)
Icore_lim (wafer level test only)
950 1300
mA
PMOS on Resistance
NMOS on Resistance
Frequency (Note 4)
rDS(ON)p
rDS(ON)n
f
Iout = 200mA
Iout = 200mA
Vin = 3.7V, Vo = 1.0V, VF6 = 0.9V
275 m
140 m
1.2 MHz
Load Regulation
VOUT = 1.6V; Io = 1mA-500mA
.05 1
%
Line Regulation
Over VCC range
1%
VOUT Pk-Pk Ripple
VP-P
Vout = 1.6V, I = 0.4A, CCM
Discontinous Mode Operation
5 mV
10 mV
System Accuracy
Over Temperature
Room Temperature
-1 2 %
-1 1 %
Under Voltage Threshold (Note 5)
Rising, as % of nominal VOUT
94 %
Falling, as % of nominal VOUT
86 %
Over Voltage threshold
Rising, as % of nominal VOUT
114 %
Falling, as % of nominal VOUT
106 %
Start-up Time
Ring Damping Switch Resistance
LINEAR REGULATORS
tst
Ron(RD)
From Enable Active @ Io = 10mA; Vo = 1.6V
1.3 ms
50 75
Input Voltage
LVCC Connected to PVCC
2.76 5.5 V
Not connected to PVCC
1.70 3.5 V
Output Voltage
VSRAM
1.1 V
VPLL
1.3 V
3 FN9171.1

No Preview Available !

ISL6271A
Electrical Specifications
PARAMETER
Operating
as shown
iCn oFnigduitrioen1s9, ,UTnylpeiscsalOAthpeprliwcaisteioNn oCteirdcu; iTt:AV=ou-2t 5=°C1.6toV,8I5O°UCT,
PVCC = VCC = 3.7V.
= 0mA (Continued)
Component
values
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Output Tolerance
Iout = 1mA
-2.5 2.5 %
Maximum Average Output Current
I_SRAM
50 mA
I_PLL
40 mA
Current Limit
Ildo_lim Each LDO regulator
120 300
%
(Note 7)
Line Regulation
LVCC = 1.7-5.5V
0.25 %
Load Regulation
Io = 1 to 25mA
.5 %
Undervoltage Threshold
Rising - % of VPLL, VSRAM
91 %
Falling - % of VPLL, VSRAM
86 %
Start-Up Time
SYSTEM
tst Soft-start power up to 1.3V, Csoft = 10nF 1.3 ms
Supply Current (VCC)
Supply Current (LVCC)
EN Voltage
Soft-Start Source Current
(Controlled by I2C control bits D5, D4)
Temperature Shutdown
POR/BFLT# Threshold (Note 6)
PGOOD Pull Down Resistance
VIDEN, VID2, VID3 Voltage Threshold
I2C LOGIC
IQ
IQ
ILVCC
VIH
VIL
I00
I01
I10
I11
Tr
Tf
VPOR
VPOR
Ron
VIH(VID)
VIL(VID)
Icore = No load
EN = 0V
Rising T
Falling T
Rising VCC
Falling VCC
380
25
25
2.0
0.55
3.4 4.8 6.2
6.7 9.6 12.5
16 24 32
30 47 64
130 140 150
85 95 105
2.60 2.80
3.0
2.44 2.60 2.76
700 960
2.4
1.0
µA
µA
µA
V
V
µA
µA
µA
µA
°C
°C
V
V
V
V
SCL, SDA Voltage Threshold
VIH(I2C)
VIL(I2C)
SDA Pull Down Resistance
Ron(SDA)
NOTES:
3. Guaranteed by design; correlated with statistic data for PVCC = VCC from 3.5V to 5.5V.
4. Switching frequency is a function of input, output voltage and load.
5. As a result of an over-current condition exceeding 800mA. Will result in a PGOOD fault.
6. A high rising POR tracks with a high falling POR.
7. Percentage of Maximum Average Output Current (I_SRAM or I_PLL).
2.0 V
0.55 V
132
4 FN9171.1

No Preview Available !

ISL6271A
Typical Operating Performance
Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made up of a 4.7µH drumcore with 100mof
DCR and an output capacitance of 10µF. X5R; Rcomp = 50k, Vin = 3.6V unless otherwise noted.
100%
95%
90%
85%
80%
75%
70%
65%
60%
0
Vo=1.6V
Vo=1.3V
200 400 600
Io (mA)
FIGURE 3. EFFICIENCY (Vin = 3.6V)
800
1.094
1.093
Io = 10mA
1.092
Io = 25mA
1.091
1.09
1.089
Iout = 55mA
1.088
1.087
1.086
Iout = 85mA
1.085
1.7 2.5 3.5
INPUT VOLTAGE
FIGURE 4. VSRAM LINE-LOAD REGULATION
1.309
1.308
1.307
Io = 5mA
Io = 20mA
1.306
1.305
1.304
1.303
Iout = 55mA
1.302
Iout = 65mA
1.301
1.7
2.5
3.5
INPUT VOLTAGE
FIGURE 5. SWITCHING REGULATOR EFFICIENCY
VOUT
PHASE
IOUT
50mA to 260mA load step on VOUT.
Top: Output voltage, 50mV/DIV; Phase node, 5V/DIV.;
Inductor current, 200mA/DIV, 2µs/DIV
FIGURE 6. DCM TO CCM
5
Top: phase node output voltage ripple, 10mV/DIV.
Bottom: Inductor current, 100mA/DIV, 1µs/DIV
FIGURE 7. CCM TO CCM
FN9171.1