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NOT RECPOINM-FMOEURNS-DPEEIN®IDSCLF9OO2MR0P6NDAEaTWtIaBDLSEEhSeIeGtNS
FlexiHash™ For Battery Authentication
The ISL6296 is a highly cost-effective fixed-secret hash
engine based on Intersil’s FlexiHash™ technology. The
device authentication is achieved through a
challenge-response scheme customized for low-cost
applications, where cloning via eavesdropping without
knowledge of the device’s secret code is not economically
viable. When used for its intended applications, the ISL6296
offers the same level of effectiveness as other significantly
more expensive high maintenance monetary-grade hash
algorithm and authentication schemes.
The ISL6296 has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL6296 can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
Communication with the host is achieved through a
single-wire XSD interface - (a light-weight subset of Intersil’s
ISD bus interface). The XSD bus is compatible for use with
serial ports offered by all 8250 compatible UART’s or a single
GPIO (general purpose input and output) pin of a
microprocessor.
A clone prevention solution utilizing the ISL6296 offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
replacement for a wide variety of low-cost applications.
Pinouts
ISL6296
(5 LD SOT-23)
TOP VIEW
VSS 1
N/C 2
VDD 3
5 XSD
4 TIO
ISL6296
(8 LD 2X3 TDFN)
TOP VIEW
VSS 1
NC 2
NC 3
VDD 4
8 XSD
7 NC
6 NC
5 TIO
March 21, 2008
ISL6296
FN9201.2
Features
• Challenge-response based authentication scheme using
32-Bit challenge code and 8-Bit authentication code.
• Fast and flexible authentication process. Multi-pass
authentication can be used to achieve the highest security
level if necessary.
• 16x8 OTP ROM stores up to three sets of 32-Bit
host-selectable secrets with additional programmable
memory for storage of up to 48 bits of ID code and/or pack
information.
• FlexiHash engine uses two sets of 32-Bit secrets for
authentication code generation.
• Non-unique mapping of the secret key to an 8-Bit
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1).
• Supports 1-cell Li-ion/Li-Poly and 3-cell series NiMH
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus.
• XSD single-wire host bus interface communicates with all
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps.
• True “Zero Power” Sleep mode - (automatically entered
after a bus inactivity time-out period)
• 5 Ld SOT-23 and 8 Ld TDFN (2mmx3mm) packages
• -25°C to +85°C operating temperature range
• Pb-free available (RoHS compliant)
Applications
• Battery Pack Authentication
• Printer Cartridges
• Add-on Accessories
• Other Non-Monetary Authentication Applications
Related Literature
• Application Note AN1165 “ISL6296 Evaluation Kit”
• Application Note AN1166 “FlexiHash™ Engine Algorithm”
• Application Note AN1167 “Implementing XSD Host Using
a GPIO”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2007, 2008. All Rights Reserved.
FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

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ISL6296
Ordering Information
PART NUMBER
(Note 1)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
Tape and Reel
PKG.
DWG. #
ISL6296DHZ-T
296Z
-25 to +85 5 Ld SOT-23 Tape and Reel (Pb-free)
P5.064
ISL6296DRZ-T
96Z
-25 to +85 8 Ld 2x3 TDFN Tape and Reel (Pb-free)
L8.2x3A
ISL6296DH-T
296D
-25 to +85 5 Ld SOT-23 Tape and Reel
P5.064
ISL6296EVAL1
ISL6296 Evaluation Kit
* Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2 FN9201.2
March 21, 2008

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ISL6296
Absolute Maximum Ratings (Reference to GND)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to VDD+0.5V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .4000V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .400V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-25°C to +85°C
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
SOT-23 Package (Note 2) . . . . . . . . . . 200
N/A
2x3 TDFN Package (Notes 3, 4) . . . . .
70
10.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -25°C to +85°C; VDD = 2.6V to 4.8V.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 5) TYP (Note 5) UNITS
DC CHARACTERISTICS
Supply Voltage
VDD During normal operation
During OTP ROM programming
2.6 - 4.8 V
2.8 - 4.8 V
Run Mode Supply Current
(exclude I/O current)
IDD VDD = 4.2V
VDD = 4.8V
Sleep Mode Supply Current
IDDS VDD = 4.2V, XSD pin floating
OTP Programming Mode Supply Current IDDP For ~ 1.8ms duration per write operation
Internal Regulated Supply Voltage
VRG Observable only in test mode
Internal OTP ROM Programming Voltage VPP Observable only in test mode
POR Release Threshold
VPOR+
POR Assertion Threshold
VPOR-
XSD PIN CHARACTERISTICS
- 110 140
- 120 160
- 0.15 0.5
- 250 500
2.3 2.5
2.7
11 12
13
1.9 2.2
2.4
1.5 1.8
2.1
µA
µA
µA
µA
V
V
V
V
XSD Input Low Voltage
XSD Input High Voltage
VIL
VIH
-0.4 - 0.5 V
1.5 - VDD+ V
0.4V
XSD Input Hysteresis
VHYS
XSD Internal Pull-Down Current
IPD VDD = 2.6V
VDD = 4.2V
VDD = 4.8V
XSD Output Low Voltage
VOL IOL = 1mA
XSD Input Transition Time
tX 10% to 90% transition time
XSD Output Fall Time
tF 90% to 10%, CLOAD = 12pF
XSD Pin Capacitance
CPIN
XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables)
- 400
-
mV
- 0.8 - µA
- 1.2 2.0 µA
- 1.8 2.5 µA
- - 0.4 V
- - 2 µs
- - 50 ns
-6
- pF
Programming Bit Rate
x = 0.5 to 4
2.89
-
23.12
kHz
3 FN9201.2
March 21, 2008

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ISL6296
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -25°C to +85°C; VDD = 2.6V to 4.8V. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 5) TYP (Note 5) UNITS
XSD Input Deglitch Time
TWDG Pulse width narrower than the deglitch time will not 7 - 20 µs
cause the device to wake up
Device Wake-Up Time
TWKE From falling-edge of break command issued by host to 35 60 100 µs
falling-edge of break command returned by device
Device Sleep Wait Time
TSLP From when the ‘11’ Opcode is detected to the shut-off
of the internal regulator
4
-
- µs
Auto-Sleep Time-Out Period
TASLP From the last transition detected on the XSD bus to the 0.9
-
1.1
s
device going into sleep mode
OTP ROM Write Time
TEEW From the last BT of the 2nd write data frame to when
device is ready to accept the next instruction
-
1.8 1.9
ms
Hash Calculation Time
THASH From the last BT of the Challenge Code Word from the
host to the Authentication Code being available for read
-
1
- BT
Soft-Reset Time
TSRST From the last BT of the Soft-Reset instruction issued by
-
-
30 µs
the host to the falling-edge of break command returned
by device
AC CHARACTERISTICS
Oscillator Clock Frequency
Charge Pump Clock Frequency
fOSC Internal bus reference clock
505 532 560 kHz
fCP Internal high speed clock (observable only in test mode)
Low-speed mode
3.6 5
6 MHz
High-speed mode
16 20
24 MHz
Pin Descriptions
PIN NUMBER PIN NAME
DESCRIPTION
1
VSS
System ground.
2 NC No connection.
3
VDD
Supply voltage.
4 TIO Production test I/O pin. Used only during production testing. Must be left floating during normal operation.
5
XSD
Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input and an open-drain
output. An appropriate pull-up resistor is required on the host side.
4 FN9201.2
March 21, 2008

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ISL6296
Typical Applications
PACK+
XSD
PACK-
R1
100Ω XSD ISL6296 VDD
D1
5.1V
VSS
R2
100Ω
C1
0.1µF
PROTECTION
FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE BATTERY
PACK+
XSD
PACK-
R1
100Ω XSD ISL6296 VDD
D1
5.1V
VSS
C1
0.1µF
PROTECTION
FIGURE 2. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE XSD BUS
Block Diagram
VDD
XSD
POR/2.5V
REGULATOR
XSD
COMM
INTERFACE
AUTH
SESL
CHLG
FLEXIHASH+
ENGINE
MSCR
STAT
OSCILLATOR
ANALOG
DIGITAL
DCFG (1 BYTE)
DTRM (1 BYTE)
SECRET #1
(4 BYTES)
SECRET #2
(4 BYTES)
SECRET #3
(4 BYTES)
GENERAL PURPOSE
(2 BYTES)
16 BYTES
OTPROM
CONTROL/STATUS/
TEST INTERFACE
TIO
VSS
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
5
FN9201.2
March 21, 2008