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®
Data Sheet
March 30, 2006
ISL6594D
FN9282.0
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The ISL6594D is high frequency MOSFET driver specifically
designed to drive upper and lower power N-Channel
MOSFETs in a synchronous rectified buck converter
topology. This driver combined with the ISL6594D Digital
Multi-Phase Buck PWM controller and N-Channel MOSFETs
forms a complete core-voltage regulator solution for
advanced microprocessors.
The ISL6594D drives both upper and lower gates over a
range of 4.5V to 13.2V. This drive-voltage provides the
flexibility necessary to optimize applications involving trade-
offs between gate charge and conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6594D includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted.
The ISL6594D also features an input that recognizes a high-
impedance state, working together with Intersil multi-phase
PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the schottky diode that may
be utilized in a power system to protect the load from
negative output voltage damage.
Ordering Information
PART NUMBER PART
TEMP. PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL6594DCBZ 6594DCBZ 0 to 85 8 Ld SOIC
M8.15
ISL6594DCBZ-T 6594DCBZ 8 Ld SOIC Tape and Reel
ISL6594DCRZ 94DZ
0 to 85 10 Ld 3x3 DFN L10.3x3
ISL6594DCRZ-T 94DZ
10 Ld 3x3 DFN Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Pin-to-pin Compatible with ISL6596
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Optimized for 3.3V PWM Input
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6594DCB (8LD SOIC)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 PVCC
6 VCC
5 LGATE
ISL6594D
ISL659DCR (10LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
N/C 3
PWM 4
GND 5
GND
10 PHASE
9 PVCC
8 N/C
7 VCC
6 LGATE
Block Diagram
VCC
PWM
UVCC
+5V Pre-POR OVP
FEATURES
13.6K
6.4K
POR/
CONTROL
LOGIC
ISL6594D
SHOOT-
THROUGH
PROTECTION
(LVCC)
BOOT
UGATE
PHASE
PVCC
UVCC = PVCC FOR ISL6594D
LGATE
PAD
GND
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2 FN9282.0
March 30, 2006

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Typical Application - 4 Channel Converter Using ISL6592 and ISL6594D Gate Drivers
+12V
ISL6594D
+5V
1 UGATE PHASE 8
2 BOOT PVCC 7
3 PWM
VCC 6
4 GND LGATE 5
+3.3V
FROM µP
TO µP
FAULT
OUTPUTS
I2C I/F
BUS
VDD
V12_SEN
ISL6592
GND
OUT1
VID4
OUT2
VID3
VID2
VID1
VID0
VID5
LL0
LL1
ISEN1
OUT3
OUT4
ISEN2
OUT5
OUT6
ISEN3
OUTEN
OUT7
OUT8
VCC_PWRGD
ISEN4
OUT9
RESET_N
OUT10
ISEN5
FAULT1
OUT11
FAULT2
OUT12
ISEN6
SDA
TEMP_SEN
SCL
SADDR
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
ISL6594D
1 UGATE PHASE 8
2 BOOT PVCC 7
3 PWM
VCC 6
4 GND LGATE 5
ISL6594D
1 UGATE PHASE 8
2 BOOT PVCC 7
3 PWM
VCC 6
4 GND LGATE 5
ISL6594D
1 UGATE PHASE 8
2 BOOT PVCC 7
3 PWM
VCC 6
4 GND LGATE 5
RTHERM
Vout
RTN

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ISL6594D
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V))
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
IVCC
IVCC
IPVCC
IPVCC
ISL6594D, fPWM = 300kHz, VVCC = 12V
ISL6594D, fPWM = 1MHz, VVCC = 12V
ISL6594D, fPWM = 300kHz, VPVCC = 12V
ISL6594D, fPWM = 1MHz, VPVCC = 12V
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT (See Timing Diagram on Page 6)
Input Current
PWM Rising Threshold (Note 4)
IPWM
VPWM = 3.3V
VPWM = 0V
VCC = 12V
PWM Falling Threshold (Note 4)
VCC = 12V
Typical Three-State Shutdown Window
VCC = 12V
Three-State Lower Gate Falling Threshold
VCC = 12V
Three-State Lower Gate Rising Threshold
VCC = 12V
Three-State Upper Gate Rising Threshold
VCC = 12V
Three-State Upper Gate Falling Threshold
VCC = 12V
Shutdown Holdoff Time
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
tTSSHD
tRU
tRL
VPVCC = 12V, 3nF Load, 10% to 90%
VPVCC = 12V, 3nF Load, 10% to 90%
MIN
-
-
-
-
6.1
4.7
-
-
-
-
1.23
-
-
-
-
-
-
-
TYP
4.5
5
7.5
8.5
6.4
5.0
400
-350
1.70
1.30
-
1.18
0.76
2.36
1.96
245
26
18
MAX UNITS
- mA
- mA
- mA
- mA
6.7 V
5.3 V
-
-
-
-
1.82
-
-
-
-
-
-
-
µA
µA
V
V
V
V
V
V
V
ns
ns
ns
4 FN9282.0
March 30, 2006

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ISL6594D
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT (Note 4)
tFU
tFL
tPDHU
tPDHL
tPDLU
tPDLL
tPDTS
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
- 18 - ns
- 12 - ns
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
Upper Drive Source Current
IU_SOURCE VPVCC = 12V, 3nF Load
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
Upper Drive Sink Current
IU_SINK VPVCC = 12V, 3nF Load
Upper Drive Sink Impedance
RU_SINK 150mA Sink Current
Lower Drive Source Current
IL_SOURCE VPVCC = 12V, 3nF Load
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
Lower Drive Sink Current
IL_SINK VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
- 1.25 -
1.4 2.0 3.0
-2-
0.9 1.65 3.0
-2-
0.85 1.3
2.2
-3-
0.60 0.94 1.35
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under Description for guidance in choosing the capacitor value.
- 3, 8 N/C No Connection.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under Description for further details. Connect this pin to the PWM output of the
controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN9282.0
March 30, 2006