ISL6884.pdf 데이터시트 (총 13 페이지) - 파일 다운로드 ISL6884 데이타시트 다운로드

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®
Data Sheet
March 9, 2006
ISL6884
FN9265.0
CCFL Brightness Controller
ISL6884 controls Pulse Width Modulated Dimming for up to
8 inverters to supply power to up to 40 Cold Cathode
Fluorescent Lamps (CCFL) for back lighting in large LCD
displays.
The ISL6884 brightness controller provides an I2C interface
for dimming control, enable, status, and brightness balance.
The duty cycle of all 8 DPWM outputs is adjusted with a
Master Brightness Control register. The duty cycle of each of
the 8 DPWM outputs can be offset from the master
brightness to adjust for uniform brightness.
The PWM dimming frequency can be set by an internal,
adjustable oscillator or synchronized to an external source to
minimize interference with video.
ISL6884’s slave address is:
• 1101_1111 for reading
• 1101_1110 for writing
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG.
DWG. #
ISL6884IAZ
(See Note)
-40 to 85
20 Ld SSOP
(Pb-free)
M20.15
ISL6884IAZ-T
(See Note)
-40 to 85
20 Ld SSOP Tape M20.15
and Reel
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Wide Supply Voltage Range of 3.0V to 5.5V
• Dimming
- I2C dimming control input
- PWM dimming can be synchronized to an external
source or set by an internal, adjustable oscillator.
- 8 channel dimming allows the user to balance the
brightness of the CCFL lamps via I2C control
- User programmable fault time out
• User Programmable Fault Time Out
• I2C Status Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6884
(20 LD SSOP)
TOP VIEW
LAMP_ON 1
TESTEN 2
GNDPLL 3
PLL1 4
EN 5
DPWM_SYNC 6
OSCTEST 7
SCL 8
SDA 9
GND 10
20 VDD
19 REGCAP
18 DPWM_8
17 DPWM_7
16 DPWM_6
15 DPWM_5
14 DPWM_4
13 DPWM_3
12 DPWM_2
11 DPWM_1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
ISL6884
VDD
GND
EN
BGREF
I2C ENABLE
POR
2.5V REG
ENAB
fault timer
STATUS
DPWM SYNC
PLL1
GNDPLL
SDA
SCL
PWM
DIMMING
PLL
8 CH DPWM GEN
OSC
I2C
interface
BRIGHTNESS
STATUS
ENABLE (I2C)
8
CCFL Brightness Controller
REGCAP
LAMP ON
DPWM_8
DPWM_7
DPWM_6
DPWM_5
DPWM_4
DPWM_3
DPWM_2
DPWM_1
TESTEN
OSCTEST
2 FN9265.0
March 9, 2006

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ISL6884
Simplified System Diagram - Central Controller and Multiple Local Controllers
ISL6884
SYSTEM I2C
CENTRAL
CONTROLLER
SCL
SDA
MASTER
DPWM
ISL6882
LOCAL
CONTROLLER
DRIVE
IFB
VFB
CCFL
CCFL
CCFL
PHASE MODULATION OUT
DRIVE ISL6883 PM IN
DRIVER
DPWM
ISL6882
LOCAL
CONTROLLER
DRIVE
IFB
VFB
CCFL
CCFL
CCFL
PHASE MODULATION OUT
DRIVE ISL6883 PM IN
DRIVER
DPWM
ISL6882
LOCAL
CONTROLLER
DRIVE
IFB
VFB
CCFL
CCFL
CCFL
PHASE MODULATION OUT
CONFIDENTIALDPWM
ISL6882
LOCAL
CONTROLLER
DRIVE
IFB
VFB
PHASE MODULATION OUT
CCFL
CCFL
CCFL
DRIVE
ISL6883
DRIVER
PM IN
DRIVE ISL6883 PM IN
DRIVER
3 FN9265.0
March 9, 2006

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ISL6884 Application Schematic
Use these parts
to adjust the
internal DPWM
oscillator
frequency
external
hardware
enable
3300
1uF 2200
0.47uF
73.2K
This is the LPF for
the DPWM PLL
0.1uF
ISL6884
LAMPON
output from
ISL6882
LAMP_ON
TESTEN
GNDPLL
PLL1
EN
DPWM_SYNC
OSCTEST
SCL
SDA
GND
1 20
2 19
3 18
4 17
5 16
6 ISL6884 15
7 14
8 13
9 12
10 11
VDD
REGCAP
DPWM_8
DPWM_7
DPWM_6
DPWM_5
DPWM_4
DPWM_3
DPWM_2
DPWM_1
VDD
to DPWM
dimming
inputs to
up to 8
ISL6882
to the system master,
other I2C devices and
pull up resisters
1uF
1uF 0.01uF
external signal to
sync DPWM
4 FN9265.0
March 9, 2006

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ISL6884
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Input/Output Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Information
Thermal Resistance (Typical, Notes 1)
20 Ld SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
θJA (°C/W)
110
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
POWER ON RESET
VDD Rising
VDD Falling
POR Hysteresis
VOLTAGE REGULATOR
PORrising
PORfalling
PORhyst
2.4 2.7 3.0 V
2.2 2.5 2.7 V
- 200 - mV
Regulated Voltage
Vreg
External Capacitor = 1µF, ESR<1
LOGIC LEVEL INPUTS (EN, DPWM_SYNC, LAMPON)
2.3 2.5 2.7 V
V In High
V In Low
Hysteresis
VIHLOGIC
VILLOGIC
Vhyst
2.6 -
-V
- - 0.8 V
- 140 - mV
Input Current
I2C
I_IN Vin = VDD
Vin = 0V
- 10 - nA
- -10 - nA
V In Low
V In High
Schmitt Trigger Input Hysteresis
V Out Low
SDA, SCL Rise Time
VIL
VIH
Vhys
VOL
Trise_I2C
I in low = 3mA
Cload = 200pF
Rpullup = 1700, 30%-70%
- - 0.3*VDD
0.7*VDD
-
-
- 0.05*VDD -
- - 0.4
- 300 -
V
V
V
V
ns
SDA, SCL Fall Time
Tfall_I2C
Cload = 200pF
Rpullup = 1700, 30%-70%
- - 300 ns
5 FN9265.0
March 9, 2006