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®
Data Sheet
June 15, 2006
X5083
FN8127.3
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point. RESET is
asserted until VCC returns to the proper operating level and
stabilizes. Five industry standard VTRIP thresholds are
www.DataSheet4U.coamvailable, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
Pinouts
8 LD TSSOP
RESET
VCC
CS/WDI
SO
18
2
3
X5083
7
6
45
SCK
SI
VSS
WP
8 LD SOIC, 8 LD PDIP
CS/WDI
SO
WP
VSS
18
27
3 X5083 6
45
VCC
RESET
SCK
SI
Features
• Low VCC detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lockmemory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
• Built-in inadvertent write protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
X5083
Block Diagram
VCC
CS/WDI
SI
SO
SCK
WP
VTRIP
+
-
POR AND LOW
VOLTAGE RESET
GENERATION
RESET & WATCHDOG
TIMEBASE
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
RESET
COMMAND
DECODE &
CONTROL
LOGIC
PROTECT LOGIC
STATUS
REGISTER
EEPROM
ARRAY
8KBITS
RESET (X5083)
X5083
STANDARD VTRIP LEVEL
4.63V (+/-2.5%)
4.38V (+/-2.5%)
2.93V (+/-2.5%)
2.63V (+/-2.5%)
SUFFIX
-4.5A
-4.5
-2.7A
-2.7
See “Ordering Information” on page 3 for
more details
For Custom Settings, call Intersil.
2 FN8127.3
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X5083
Ordering Information
PART NUMBER RESET
(ACTIVE LOW)
PART MARKING
X5083P-4.5A
X5083P AL
X5083PZ-4.5A (Note)
X5083P ZAL
X5083PI-4.5A
X5083P AM
X5083PIZ-4.5A (Note)
X5083P ZAM
X5083S8-4.5A
X5083 AL
X5083S8Z-4.5A (Note)
X5083 ZAL
X5083S8I-4.5A*
X5083 AM
VCC RANGE (V)
4.5-5.5
VTRIP RANGE
4.5-4.75
TEMPERATURE
RANGE (°C)
PACKAGE
0 to 70
8 Ld PDIP
0 to 70
8 Ld PDIP* (Pb-free)
-40 to 85 8 Ld PDIP
-40 to 85 8 Ld PDIP* (Pb-free)
0 to 70
8 Ld SOIC
0 to 70
8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC
X5083S8IZ-4.5A* (Note)
X5083V8-4.5A
X5083V8Z-4.5A (Note)
X5083 ZAM
583 AL
583 ZAL
-40 to 85
0 to 70
0 to 70
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
X5083V8I-4.5A
X5083V8IZ-4.5A (Note)
X5083P
583 AM
583 ZAM
X5083P
4.5-5.5
4.25-4.5
-40 to 85
-40 to 85
0 to 70
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld PDIP
X5083PZ (Note)
X5083PI
X5083PIZ (Note)
X5083P Z
X5083P I
X5083P ZI
0 to 70
-40 to 85
-40 to 85
8 Ld PDIP* (Pb-free)
8 Ld PDIP
8 Ld PDIP* (Pb-free)
X5083SI
X5083S8
X5083S8Z (Note)
X5083 I
X5083
X5083 Z
-40 to 85
0 to 70
0 to 70
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC (Pb-free)
X5083S8I*
X5083S8IZ* (Note)
X5083V8
X5083V8Z (Note)
X5083V8I
X5083V8IZ (Note)
X5083P-2.7A
X5083 I
X5083 ZI
583
583 Z
583 I
583 IZ
X5083P AN
2.7-5.5
2.85-3.0
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld PDIP
X5083PZ-2.7A (Note)
X5083PI-2.7A
X5083PIZ-2.7A (Note)
X5083P ZAN
X5083P AP
X5083P ZAP
0 to 70
-40 to 85
-40 to 85
8 Ld PDIP* (Pb-free)
8 Ld PDIP
8 Ld PDIP* (Pb-free)
X5083S8-2.7A
X5083S8Z-2.7A (Note)
X5083S8I-2.7A
X5083 AN
X5083 ZAN
X5083 AP
0 to 70
0 to 70
-40 to 85
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
X5083S8IZ-2.7A* (Note)
X5083V8-2.7A
X5083V8Z-2.7A (Note)
X5083 ZAP
583 AN
583 ZAN
-40 to 85
0 to 70
0 to 70
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
X5083V8I-2.7A
X5083V8IZ-2.7A (Note)
583 AP
583 ZAP
-40 to 85
-40 to 85
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
PKG.
DWG. #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
3 FN8127.3
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X5083
Ordering Information (Continued)
PART NUMBER RESET
(ACTIVE LOW)
PART MARKING
X5083P-2.7
X5083P F
VCC RANGE (V)
2.7-5.5
VTRIP RANGE
2.55-2.7
TEMPERATURE
RANGE (°C)
PACKAGE
0 to 70
8 Ld PDIP
PKG.
DWG. #
MDP0031
X5083PZ-2.7 (Note)
X5083P ZF
0 to 70
8 Ld PDIP* (Pb-free)
MDP0031
X5083PI-2.7
X5083P G
-40 to 85 8 Ld PDIP
MDP0031
X5083PIZ-2.7 (Note)
X5083P ZG
-40 to 85 8 Ld PDIP* (Pb-free)
MDP0031
X5083S8-2.7*
X5083 F
0 to 70
8 Ld SOIC
MDP0027
X5083S8Z-2.7* (Note)
X5083 ZF
0 to 70
8 Ld SOIC (Pb-free)
MDP0027
X5083S8I-2.7*
X5083 G
-40 to 85 8 Ld SOIC
MDP0027
X5083S8IZ-2.7* (Note)
X5083 ZG
-40 to 85 8 Ld SOIC (Pb-free)
MDP0027
X5083V8-2.7
583 F
0 to 70
8 Ld TSSOP
M8.173
X5083V8Z-2.7 (Note)
583 FZ
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X5083V8I-2.7
583G
-40 to 85 8 Ld TSSOP
M8.173
X5083V8IZ-2.7 (Note)
583 GZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Description
PIN
(SOIC/
PDIP)
1
2
5
6
3
4
8
7
PIN
TSSOP
3
4
7
8
5
6
2
1
NAME
FUNCTION
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless
a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the
device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW
transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a
HIGH to LOW transition within the watchdog time out period results in RESET going active.
SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the
serial clock (SCK) clocks the data out.
SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising
edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches
in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO
pin.
WP Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.
VSS
VCC
RESET
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.
RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the
selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on
power-up at about 1V and remains active for 250ms after the power supply stabilizes.
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X5083
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. RESET
active also blocks communication to the device through the
SPI interface. When VCC exceeds the device VTRIP value for
200ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code. While VCC < VTRIP
communications to the device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the VCC level and
asserts RESET if supply voltage falls below a preset
minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition and terminates any SPI communication in
progress. The RESET signal remains active until the voltage
drops below 1V. It also remains active until VCC returns and
exceeds VTRIP for 200ms.
When VCC falls below VTRIP, any communications in
progress are terminated and communications are inhibited
until VCC exceeds VTRIP for tPURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle
the CS/WDI pin periodically to prevent a RESET signal. The
CS/WDI pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits with no action taken by the microprocessor
these bits remain unchanged, even after total power failure.
VCC Threshold Reset Procedure
The X5083 is shipped with a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or if higher precision is
needed in the VTRIP value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When
VTRIP is reset, the new VTRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the Vcc pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of data 00h to address 03h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 03h.
5 FN8127.3
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