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®
Data Sheet
X5163, X5165
June 1, 2006
FN8128.3
CPU Supervisor with 16Kbit SPI EEPROM
Description
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval, the
device activates the RESET/RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system when
VCC falls below the minimum VCC trip point. RESET/RESET is
asserted
www.DataSheet4U.com
until
VCC
returns
to
proper
operating
level
and
stabilizes. Five industry standard VTRIP thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom requirements
or to fine-tune the threshold for applications requiring higher
precision.
Pinouts
CS/WDI
SO
WP
VSS
8 Ld SOIC/PDIP
X5163, X5165
18
27
3 X5163, X5165 6
45
VCC
RESET/RESET
SCK
SI
Features
• Selectable watchdog timer
• Low VCC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
- Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 16kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lockprotection
- In-circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply operation
• Available packages: 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
CS/WDI
SO
NC
NC
NC
WP
VSS
14 Ld TSSOP
X5163, X5165
1 14
2 13
3 12
4 11
5 10
69
78
VCC
RESET/RESET
NC
NC
NC
SCK
SI
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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X5163, X5165
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5163P
X5163P
X5165P
X5165P
VCC RANGE
(V)
4.5-5.5
TEMP
VTRIP RANGE RANGE (°C) PACKAGE
4.25-4.5
0 to 70 8 Ld PDIP
PKG.
DWG. #
MDP0031
X5163PZ (Note) X5163P Z X5165PZ (Note) X5165P Z
X5163PI
X5163P I
X5165PI
X5165P I
0 to 70 8 Ld PDIP**
(Pb-free)
-40 to 85 8 Ld PDIP
MDP0031
MDP0031
X5163PIZ (Note) X5163P Z I X5165PIZ (Note) X5165P Z I
X5163S8*
X5163
X5165S8*
X5165
-40 to 85 8 Ld PDIP**
(Pb-free)
0 to 70 8 Ld SOIC
MDP0031
MDP0027
X5163S8Z* (Note) X5163 Z
X5163S8I*
X5163S8IZ*
(Note)
X5163 I
X5163 Z I
X5165S8Z*
(Note)
X5165S8I*
X5165S8IZ*
(Note)
X5165 Z
X5165 I
X5165 Z I
0 to 70 8 Ld SOIC
(Pb-free)
-40 to 85 8 Ld SOIC
-40 to 85 8 Ld SOIC
(Pb-free)
MDP0027
MDP0027
MDP0027
X5163V14*
X5163V14Z*
(Note)
X5163V
X5163V Z
X5165V14*
X5165V14Z*
(Note)
X5165V
X5165V Z
0 to 70
0 to 70
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
X5163V14I*
X5163V I
X5165V14I*
X5165V I
X5163V14IZ*
(Note)
X5163V Z I X5165V14IZ*
(Note)
X5165V Z I
X5163P-2.7
X5163P F X5165P-2.7
X5165P F
X5163PZ-2.7
(Note)
X5163P Z F X5165PZ-2.7
(Note)
X5165P Z F
X5163PI-2.7
X5163P G X5165PI-2.7
X5165P G
X5163PIZ-2.7
(Note)
X5163P Z G X5165PIZ-2.7
(Note)
X5165P Z G
X5163S8-2.7* X5163 F
X5165S8-2.7* X5165 F
X5163S8Z-2.7* X5163 Z F
(Note)
X5165S8Z-2.7* X5165 Z F
(Note)
X5163S8I-2.7* X5163 G
X5165S8I-2.7* X5165 G
X5163S8IZ-2.7* X5163 Z G X5165S8IZ-2.7* X5165 Z G
(Note)
(Note)
X5163V14-2.7* X5163V F X5165V14-2.7* X5165V F
X5163V14Z-2.7* X5163V Z F X5165V14Z-2.7* X5165V Z F
(Note)
(Note)
X5163V14I-2.7* X5163V G X5165V14I-2.7* X5165V G
X5163V14IZ-2.7* X5163V Z G X5165V14IZ-2.7* X5165V Z G
(Note)
(Note)
X5163P-2.7A
X5163P AN X5165P-2.7A
X5165P AN
2.7-5.5
2.7-5.5
2.55-2.7
2.85-3.0
-40 to 85 14 Ld TSSOP M14.173
-40 to 85 14 Ld TSSOP M14.173
(Pb-free)
0 to 70 8 Ld PDIP
MDP0031
0 to 70 8 Ld PDIP** MDP0031
(Pb-free)
-40 to 85 8 Ld PDIP
MDP0031
-40 to 85 8 Ld PDIP** MDP0031
(Pb-free)
0 to 70 8 Ld SOIC MDP0027
0 to 70 8 Ld SOIC
(Pb-free)
MDP0027
-40 to 85 8 Ld SOIC MDP0027
-40 to 85 8 Ld SOIC
(Pb-free)
MDP0027
0 to 70 14 Ld TSSOP M14.173
0 to 70 14 Ld TSSOP M14.173
(Pb-free)
-40 to 85 14 Ld TSSOP M14.173
-40 to 85 14 Ld TSSOP M14.173
(Pb-free)
0 to 70 8 Ld PDIP
MDP0031
X5163PZ-2.7A
(Note)
X5163PI-2.7A
X5163P Z AN X5165PZ-2.7A
(Note)
X5163P AP X5165PI-2.7A
X5165P Z AN
X5165P AP
0 to 70 8 Ld PDIP**
(Pb-free)
-40 to 85 8 Ld PDIP
MDP0031
MDP0031
X5163PIZ-2.7A
(Note)
X5163S8-2.7A*
X5163P Z AP X5165PIZ-2.7A
(Note)
X5163 AN X5165S8-2.7A
X5165P Z AP
X5165 AN
-40 to 85 8 Ld PDIP**
(Pb-free)
0 to 70 8 Ld SOIC
MDP0031
MDP0027
2 FN8128.3
June 1, 2006

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X5163, X5165
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
X5163S8Z-2.7A* X5163 Z AN X5165S8Z-2.7A X5165 Z AN
(Note)
(Note)
VCC RANGE
(V)
2.7-5.5
TEMP
VTRIP RANGE RANGE (°C) PACKAGE
2.85-3.0
0 to 70 8 Ld SOIC
(Pb-free)
PKG.
DWG. #
MDP0027
X5163S8I-2.7A X5163 AP X5165S8I-2.7A X5165 AP
-40 to 85 8 Ld SOIC MDP0027
X5163S8IZ-2.7A X5163 Z AP X5165S8IZ-2.7A X5165 Z AP
(Note)
(Note)
-40 to 85 8 Ld SOIC
(Pb-free)
MDP0027
X5163V14-2.7A X5163V AN X5165V14-2.7A X5165V AN
0 to 70 14 Ld TSSOP M14.173
X5163V14Z-2.7A X5163V Z AN X5165V14Z-2.7A X5165V Z AN
(Note)
(Note)
0 to 70 14 Ld TSSOP M14.173
(Pb-free)
X5163V14I-2.7A X5163V AP X5165V14I-2.7A X5165V AP
-40 to 85 14 Ld TSSOP M14.173
X5163V14IZ-2.7A X5163V Z AP X5165V14IZ-2.7A X5165V Z AP
(Note)
(Note)
-40 to 85 14 Ld TSSOP M14.173
(Pb-free)
X5163P-4.5A
X5163P AL X5165P-4.5A
X5165P AL
4.5-5.5
4.5-4.75
0 to 70 8 Ld PDIP
MDP0031
X5163PZ-4.5A
(Note)
X5163P Z AL X5165PZ-4.5A
(Note)
X5165P Z AL
0 to 70 8 Ld PDIP** MDP0031
(Pb-free)
X5163PI-4.5A X5163P AM X5165PI-4.5A X5165P AM
-40 to 85 8 Ld PDIP
MDP0031
X5163PIZ-4.5A X5163P Z AM X5165PIZ-4.5A X5165P Z AM
(Note)
(Note)
-40 to 85 8 Ld PDIP** MDP0031
(Pb-free)
X5163S8-4.5A X5163 AL X5165S8-4.5A X5165 AL
0 to 70 8 Ld SOIC MDP0027
X5163S8Z-4.5A X5163 Z AL X5165S8Z-4.5A X5165 Z AL
(Note)
(Note)
0 to 70 8 Ld SOIC
(Pb-free)
MDP0027
X5163S8I-4.5A X5163 AM X5165S8I-4.5A X5165 AM
-40 to 85 8 Ld SOIC MDP0027
X5163S8IZ-4.5A X5163 Z AM X5165S8IZ-4.5A X5165 Z AM
(Note)
(Note)
-40 to 85 8 Ld SOIC
(Pb-free)
MDP0027
X5163V14-4.5A X5163V AL X5165V14-4.5A X5165V AL
0 to 70 14 Ld TSSOP M14.173
X5163V14Z-4.5A X5163V Z AL X5165V14Z-4.5A X5165V Z AL
(Note)
(Note)
0 to 70 14 Ld TSSOP M14.173
(Pb-free)
X5163V14I-4.5A X5163V AM X5165V14I-4.5A X5165V AM
-40 to 85 14 Ld TSSOP M14.173
X5163V14IZ-4.5A X5163V Z AM X5165V14IZ-4.5A X5165V Z AM
(Note)
(Note)
-40 to 85 14 Ld TSSOP M14.173
(Pb-free)
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN8128.3
June 1, 2006

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X5163, X5165
Block Diagram
WP
SI
SO
SCK
CS/WDI
VCC
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
4K Bits
4K Bits
8K Bits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5163 = RESET
X5165 = RESET
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
11
22
36
47
58
69
7 13
8 14
3-5,10-12
NAME
FUNCTION
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH
to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW
transition within the watchdog time out period results in RESET/RESET going active.
SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
VSS Ground
SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the Watchdog Timer is
enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out
period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power-
up at 1V and remains active for 200ms after the power supply stabilizes.
VCC Supply Voltage
NC No internal connections
4 FN8128.3
June 1, 2006

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X5163, X5165
Principles Of Operation
Power-on Reset
Application of power to the X5163, X5165 activates a Power-
on Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. When VCC
exceeds the device VTRIP value for 200ms (nominal) the
circuit releases RESET/RESET, allowing the processor to
begin executing code.
Low Voltage Monitoring
During operation, the X5163, X5165 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin LOW and setting
the WPEN bit HIGH.
VCC Threshold Reset Procedure
The X5163, X5165 has a standard VCC threshold (VTRIP)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in
the VTRIP value, the X5163, X5165 threshold may be
adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET and SO pins are left unconnected. Then
apply the programming voltage VP to both SCK and SI and
pulse CS/WDI LOW then HIGH. Remove VP and the
sequence is complete.
CS
SCK
VP
VP
SI
FIGURE 1. SET VTRIP VOLTAGE
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset,
the new VTRIP is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, AND
THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage VP to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP
and the sequence is complete.
CS
SCK
VCC
VP
SI
FIGURE 2. RESET VTRIP VOLTAGE
5 FN8128.3
June 1, 2006