X9260.pdf 데이터시트 (총 23 페이지) - 파일 다운로드 X9260 데이타시트 다운로드

No Preview Available !

®
Data Sheet
X9260
Dual Supply/Low Power/256-Tap/SPI bus
August 29, 2006
FN8170.3
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current <5µA Max
• VCC: 2.7V to 5.5V Operation
50kΩ, 100kΩ Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24 Ld SOIC
• Low Power CMOS
www.DataSheet4U.com Power Supply VCC = 2.7V to 5.5V
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
• Pb-Free Plus Anneal Available (RoHS Compliant)
FUNCTIONAL DIAGRAM
DESCRIPTION
The X9260 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four nononvolatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the
contents of the default Data Register (DR0) to the
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
VCC
V+
RH0
RH1
SPI
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power-on Recall
Wiper Counter
Registers (WCR)
Data Registers
(DR0-DR3)
VSS
V- RW0 RL0 RW1 RL1
50kΩ or 100kΩ versions
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners

No Preview Available !

X9260
Ordering Information
PART NUMBER
X9260TS24I
PART
MARKING
X9260TS I
POTENTIOMETER
ORGANIZATION TEMPERATURE
VCC LIMITS (V)
(kΩ)
RANGE (°C)
PACKAGE
5 ±10%
100 -40 to +85 24 Ld SOIC (300 mil)
PKG. DWG. #
M24.3
X9260TS24IZ (Note) X9260TS ZI
-40 to +85
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260US24
X9260US
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9260US24Z (Note) X9260US Z
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260TS24I-2.7
X9260TS G
2.7 to 5.5
100
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9260TS24IZ-2.7 (Note) X9260TS ZG
-40 to +85
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9260US24-2.7
X9260US F
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9260US24Z-2.7 (Note) X9260US ZF
0 to +70
24 Ld SOIC (300 mil)
(Pb-free)
M24.3
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
RH0 RL0RW0
HOLD
CS
SCK
SO
SI
A0
A1
WP
VCC
V+
INTERFACE
AND
CONTROL
CIRCUITRY
8
Data
Power-on
Recall
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
50KΩ and 100KΩ
256-taps
Power-on
Recall
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VSS V-
RL1 RH1 RW1
2 FN8170.3
August 29, 2006

No Preview Available !

X9260
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
PIN CONFIGURATION
SO
A0
NC
NC
NC
V+
VCC
RL0
RH0
RW0
CS
WP
SOIC
1 24
2 23
3 22
4 21
5 20
6 19
7 X9260 18
8 17
9 16
10 15
11 14
12 13
HOLD
SCK
NC
NC
NC
V-
VSS
RW1
RH1
RL1
A1
SI
3 FN8170.3
August 29, 2006

No Preview Available !

X9260
PIN ASSIGNMENTS
Pin
(SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
SO
A0
NC
NC
NC
V+
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
VSS
V-
NC
NC
NC
SCK
HOLD
Function
Serial Data Output for SPI bus
Device Address for SPI bus.
No Connect.
No Connect.
No Connect.
Analog Supply Voltage (Positive)
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for SPI bus.
Hardware Write Protect
Serial Data Input for SPI bus
Device Address for SPI bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
Analog Supply Voltage (Negative)
No Connect
No Connect
No Connect
Serial Clock for SPI bus
Device select. Pause the SPI serial bus.
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9260.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9260.
CHIP SELECT (CS)
When CS is HIGH, the X9260 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
4 FN8170.3
August 29, 2006

No Preview Available !

X9260
standby state. CS LOW enables the X9260, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of RH and
RL such that RH0 and RL0 are the terminals of POT 0
and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of RW such that RW0
is the terminals of POT 0 and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Analog Supply Voltages (V+ and V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
PRINCIPLES OF OPERATION
Serial Interface
The X9260 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9260 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
Power-up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, VCC, V+, and V- must reach their
final values within 1msecs of each other. The VCC
ramp rate spec is always in effect.
5 FN8170.3
August 29, 2006