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Data Sheet
Dual, 10-/12-/14-/16-Bit, 250 MSPS,
Digital-to-Analog Converters
AD9743/AD9745/AD9746/AD9747
FEATURES
High dynamic range, dual digital-to-analog converters (DACs)
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz
intermediate frequency (IF)
Innovative switching output stage permits useable outputs
beyond Nyquist frequency
LVCMOS inputs with dual-port or optional interleaved
single-port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full-scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS-compliant, 72-lead LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications: LMDS/MMDS, point-to-point
Instrumentation
Radio frequency (RF) signal generators, arbitrary
waveform generators
GENERAL DESCRIPTION
The AD9743/AD9745/AD9746/AD9747 are pin-compatible,
high dynamic range, dual DACs with 10-/12-/ 14-/16-bit
resolutions and sample rates of up to 250 MSPS. The devices
include specific features for direct conversion transmit applications,
including gain and offset compensation, and they interface
seamlessly with analog quadrature modulators, such as the
ADL5370.
A proprietary, dynamic output architecture permits synthesis of
analog outputs even above Nyquist by shifting energy away from
the fundamental and into the image frequency.
A serial peripheral interface (SPI) port provides full
programmability. In addition, some pin-programmable features
are offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
PID<15:0>
CMOS
INTERFACE
INTERFACE LOGIC
10
P2D<15:0>
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
16-BIT
DAC1
16-BIT
DAC2
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
Figure 1.
Rev. B
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Tel: 781.329.4700 ©2007–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9743/AD9745/AD9746/AD9747
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
DC Specifications ......................................................................... 3 
AC Specifications.......................................................................... 5 
Digital and Timing Specifications.............................................. 7 
Absolute Maximum Ratings............................................................ 8 
Thermal Resistance ...................................................................... 8 
ESD Caution.................................................................................. 8 
Pin Configurations and Function Descriptions ........................... 9 
Typical Performance Characteristics ........................................... 17 
Terminology .................................................................................... 20 
Theory of Operation ...................................................................... 21 
SPI PORT..................................................................................... 21 
General Operation of the Serial Interface ............................... 21 
REVISION HISTORY
9/15—Rev. A to Rev. B
Deleted AD9741..................................................................Universal
Changed NC to DNC .................................................... Throughout
Deleted Figure 2; Renumbered Sequentially and Table 8;
Renumbered Sequentially................................................................ 9
Changes to Figure 2.......................................................................... 9
Changes to Figure 3........................................................................ 11
Changes to Figure 4........................................................................ 13
Changes to Figure 5........................................................................ 15
Changes to Figure 12 Caption, Figure 13 Caption, Figure 15
Caption, and Figure 16 Caption ................................................... 18
Data Sheet
Instruction Byte .......................................................................... 21 
MSB/LSB Transfers .................................................................... 22 
Serial Interface Port Pin Descriptions ..................................... 22 
SPI Register Map ............................................................................ 23 
SPI Register Descriptions .............................................................. 24 
Digital Inputs and Outputs ........................................................... 25 
Input Data Timing ..................................................................... 25 
Dual-Port Mode Timing ........................................................... 25 
Single-Port Mode Timing ......................................................... 25 
SPI Port, Reset, and Pin Mode.................................................. 25 
Driving the DAC Clock Input .................................................. 26 
Full-Scale Current Generation ................................................. 26 
DAC Transfer Function ............................................................. 27 
Analog Modes of Operation ..................................................... 27 
Auxiliary DACS .......................................................................... 28 
Power Dissipation....................................................................... 28 
Outline Dimensions ....................................................................... 30 
Ordering Guide .......................................................................... 30 
Changes to Figure 19 and Figure 20............................................. 19
Changes to Figure 39 and Figure 40............................................. 28
Changes to Ordering Guide .......................................................... 31
1/14—Rev. 0 to Rev. A
Changes to Table 15 ....................................................................... 21
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 27
5/07—Revision 0: Initial Version
Rev. B | Page 2 of 30

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Data Sheet
AD9743/AD9745/AD9746/AD9747
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 1. AD9743 and AD9745
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Gain Matching (DAC1 to DAC2)
Full-Scale Output Current
Output Compliance Voltage
Output Resistance
AUXILIARY DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Voltage Range—Sink Current
Output Compliance Voltage Range—Source Current
Output Resistance
Monotonicity
REFERENCE INPUT/OUTPUT
Output Voltage
Output Voltage Temperature Coefficient
External Input Voltage Range
Input or Output Resistance
POWER SUPPLY VOLTAGES
AVDD33, DVDD33
CVDD18, DVDD18
POWER SUPPLY CURRENTS
IAVDD33
IDVDD33
ICVDD18
IDVDD18
POWER DISSIPATION
fDAC = 250 MSPS, fOUT = 20 MHz
DAC Outputs Disabled
Full Device Power-Down
OPERATING TEMPERATURE
AD9743
AD9745
Min Typ
Max Min Typ
Max Unit
10 12 Bits
±0.05
±0.10
±0.13
±0.25
LSB
LSB
±0.001
±0.001
%FSR
1.0 1.0 ppm/°C
±2.0 ±2.0 %FSR
100 100 ppm/°C
±1.0 ±1.0 %FSR
8.6 31.7 8.6 31.7 mA
−1.0 +1.0 −1.0 +1.0 V
10 10 MΩ
10
−2.0
0.8
0
1
10
10
+2.0 −2.0
1.6 0.8
1.6 0
1
10
Bits
+2.0 mA
1.6 V
1.6 V
Bits
1.2
10
1.15
5
1.2
10
1.3 1.15
5
V
ppm/°C
1.3 V
3.13 3.47 3.13 3.47 V
1.70 1.90 1.70 1.90 V
56 60
10 14
18 22
29 33
56 60 mA
11 15 mA
18 22 mA
30 34 mA
300
115
3
−40
345 305
120
3
+85 −40
350 mW
mW
mW
+85 °C
Rev. B | Page 3 of 30

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AD9743/AD9745/AD9746/AD9747
Data Sheet
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts.
Table 2. AD9745, AD9746, and AD9747
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Gain Matching (DAC1 to DAC2)
Full-Scale Output Current
Output Compliance Voltage
Output Resistance
AUXILIARY DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Voltage Range—Sink Current
Output Compliance Voltage Range—Source Current
Output Resistance
Monotonicity
REFERENCE INPUT/OUTPUT
Output Voltage
Output Voltage Temperature Coefficient
External Input Voltage Range
Input or Output Resistance
POWER SUPPLY VOLTAGES
AVDD33, DVDD33
CVDD18, DVDD18
POWER SUPPLY CURRENTS
IAVDD33
IDVDD33
ICVDD18
IDVDD18
POWER DISSIPATION
fDAC = 250 MSPS, fOUT = 20 MHz
DAC Outputs Disabled
Full Device Power-Down
OPERATING TEMPERATURE
AD9745
Min Typ
Max
12
±0.13
±0.25
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
11 15
18 22
30 34
305
120
3
−40
350
+85
AD9746
Min Typ
Max
14
±0.5
±1.0
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
12 16
18 22
31 35
310
125
3
−40
355
+85
AD9747
Min Typ
Max
16
±2.0
±4.0
±0.001
0.1
±2.0
100
±1.0
8.6 31.7
−1.0 +1.0
10
10
−2.0
0.8
0
1
10
+2.0
1.6
1.6
1.2
10
1.15
5
1.3
3.13 3.47
1.70 1.90
56 60
12 16
18 22
32 36
310
125
3
−40
355
+85
Unit
Bits
LSB
LSB
%FSR
ppm/°C
%FSR
ppm/°C
%FSR
mA
V
Bits
mA
V
V
Bits
V
ppm/°C
V
V
V
mA
mA
mA
mA
mW
mW
mW
°C
Rev. B | Page 4 of 30

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Data Sheet
AD9743/AD9745/AD9746/AD9747
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 3. AD9743 and AD9745
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 250 MSPS, fOUT = 20 MHz
fDAC = 250 MSPS, fOUT = 70 MHz
fDAC = 250 MSPS, fOUT = 180 MHz1
INTERMODULATION DISTORTION (IMD)
fDAC = 250 MSPS, fOUT = 20 MHz
fDAC = 250 MSPS, fOUT = 70 MHz
fDAC = 250 MSPS, fOUT = 180 MHz1
CROSSTALK
fDAC = 250 MSPS, fOUT = 20 MHz
fDAC = 250 MSPS, fOUT = 70 MHz
fDAC = 250 MSPS, fOUT = 180 MHz1
ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE CARRIER W-CDMA
fDAC = 245.76 MSPS, fOUT = 15.36 MHz
fDAC = 245.76 MSPS, fOUT = 61.44 MHz
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1
NOISE SPECTRAL DENSITY (NSD)
fDAC = 245.76 MSPS, fOUT = 15.36 MHz
fDAC = 245.76 MSPS, fOUT = 61.44 MHz
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1
AD9743
AD9745
Min Typ Max Min Typ Max Unit
80 82 dBc
70 70 dBc
64 66 dBc
80 86 dBc
80 80 dBc
72 74 dBc
80 80 dBc
80 80 dBc
80 80 dBc
66 76 dBc
66 76 dBc
64 72 dBc
−144
−144
−147
−155
−155
−155
dBm/Hz
dBm/Hz
dBm/Hz
1 Mix mode.
Rev. B | Page 5 of 30