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CS42426
114 dB, 192 kHz 6-Ch Codec with PLL
Features
! Six 24-bit D/A, two 24-bit A/D Converters
! 114 dB DAC / 114 dB ADC Dynamic Range
! -100 dB THD+N
! System Sampling Rates up to 192 kHz
! Integrated Low-Jitter PLL for Increased System
Jitter Tolerance
! PLL Clock or System Clock Selection
! 7 Configurable General-Purpose Outputs
! ADC High-Pass Filter for DC Offset Calibration
! Expandable ADC Channels and One-Line
Mode Support
! Digital Output Volume Control with Soft Ramp
! Digital +/-15 dB Input Gain Adjust for ADC
! Differential Analog Architecture
!www.DataSheet4U.com Supports Logic Levels between 1.8 V and 5 V
General Description
The CS42426 codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, as well as
an integrated PLL.
The CS42426 integrated PLL provides a low-jitter sys-
tem clock. The internal stereo ADC is capable of
independent channel gain control for single-ended or
differential analog inputs. All six channels of DAC pro-
vide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.
The CS42426 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.
The CS42426 is available in a 64-pin LQFP package in
both Commercial (-10° to +70° C) and Automotive
(-40° to +85° C) grades. The CDB42428 Customer
Demonstration board is also available for device evalu-
ation. Refer to “Ordering Information” on page 71.
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
MUTEC
VA AGND
GPO
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
ADC#1
ADC#2
http://www.cirrus.com
REFGND VQ FILT+ OMCK
RMCK LPFLT VLC DGND VD
Mute
Internal Voltage
Reference
Mult/Div
PLL
Control
Port
Digital Filter
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
Gain & Clip
Gain & Clip
ADC
Serial
Audio
Port
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
ADC_SCLK
VLS
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
NOVEMBER '05
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CS42426
TABLE OF CONTENTS
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1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
SPECIFIED OPERATING CONDITIONS ............................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6
ANALOG INPUT CHARACTERISTICS .................................................................................................. 7
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8
ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9
D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10
SWITCHING CHARACTERISTICS ...................................................................................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .............................................. 12
SWITCHING CHARACTERISTICS - CONTROL PORT - SPIFORMAT .......................................... 13
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15
2. PIN DESCRIPTIONS ............................................................................................................................ 16
3. TYPICAL CONNECTION DIAGRAMS .............................................................................................. 18
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ......................................................................................................................................... 20
4.2 Analog Inputs .................................................................................................................................. 20
4.2.1 Line-Level Inputs ................................................................................................................... 20
4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21
4.3 Analog Outputs ............................................................................................................................... 21
4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21
4.3.2 Interpolation Filter .................................................................................................................. 21
4.3.3 Digital Volume and Mute Control ........................................................................................... 22
4.3.4 ATAPI Specification ............................................................................................................... 22
4.4 Clock Generation ............................................................................................................................ 23
4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23
4.4.2 OMCK System Clock Mode ................................................................................................... 24
4.4.3 Master Mode ......................................................................................................................... 24
4.4.4 Slave Mode ........................................................................................................................... 24
4.5 Digital Interfaces ............................................................................................................................. 25
4.5.1 Serial Audio Interface Signals ............................................................................................... 25
4.5.2 Serial Audio Interface Formats .............................................................................................. 27
4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30
4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31
4.5.4.1 OLM Config #1 ........................................................................................................... 31
4.5.4.2 OLM Config #2 ........................................................................................................... 32
4.5.4.3 OLM Config #3 ........................................................................................................... 33
4.5.4.4 OLM Config #4 ........................................................................................................... 34
4.6 Control Port Description and Timing ............................................................................................... 35
4.6.1 SPI Mode ............................................................................................................................... 35
4.6.2 I²C Mode ................................................................................................................................ 36
4.7 Interrupts ........................................................................................................................................ 37
4.8 Reset and Power-Up ...................................................................................................................... 37
4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 38
5. REGISTER QUICK REFERENCE ........................................................................................................ 39
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Memory Address Pointer (MAP) ..................................................................................................... 42
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42
6.3 Power Control (address 02h) .......................................................................................................... 43
6.4 Functional Mode (address 03h) ...................................................................................................... 43
6.5 Interface Formats (address 04h) .................................................................................................... 45
6.6 Misc Control (address 05h) ............................................................................................................ 46
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6.7 Clock Control (address 06h) ........................................................................................................... 48
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49
6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50
6.10 Volume Transition Control (address 0Dh) .................................................................................... 51
6.11 Channel Mute (address 0Eh) ........................................................................................................ 52
6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 53
6.13 Channel Invert (address 17h) ....................................................................................................... 53
6.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) ............................................................. 53
6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55
6.16 ADC Right Channel Gain (address 1Dh) ...................................................................................... 55
6.17 Interrupt Control (address 1Eh) .................................................................................................... 55
6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56
6.19 Interrupt Mask (address 21h) ....................................................................................................... 57
6.20 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h) ............................................................................................... 57
6.21 Mutec Pin Control (address 28h) .................................................................................................. 57
6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58
7. PARAMETER DEFINITIONS ................................................................................................................ 60
8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61
8.1 ADC Input Filter .............................................................................................................................. 61
8.2 DAC Output Filter ........................................................................................................................... 61
9. APPENDIX B: PLL FILTER .................................................................................................................. 62
9.1 External Filter Components ............................................................................................................ 62
9.1.1 General .................................................................................................................................. 62
9.1.2 Capacitor Selection ............................................................................................................... 62
9.1.3 Circuit Board Layout .............................................................................................................. 63
10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64
11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66
12. PACKAGE DIMENSIONS ............................................................................................................... 70
THERMAL CHARACTERISTICS .......................................................................................................... 70
13. ORDERING INFORMATION .............................................................................................................. 71
14. REFERENCES .................................................................................................................................... 71
15. REVISION HISTORY ......................................................................................................................... 72
LIST OF FIGURES
Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 11
Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 11
Figure 3.Control Port Timing - I²C Format ................................................................................................. 12
Figure 4.Control Port Timing - SPI Format ................................................................................................ 13
Figure 5.Typical Connection Diagram ....................................................................................................... 18
Figure 6.Typical Connection Diagram using the PLL ................................................................................ 19
Figure 7.Full-Scale Analog Input ............................................................................................................... 20
Figure 8.Full-Scale Output ........................................................................................................................ 21
Figure 9.ATAPI Block Diagram (x = channel pair 1, 2, 3) ......................................................................... 22
Figure 10.Clock Generation ...................................................................................................................... 23
Figure 11.Right-Justified Serial Audio Formats ......................................................................................... 27
Figure 12.I²S Serial Audio Formats ........................................................................................................... 28
Figure 13.Left-Justified Serial Audio Formats ........................................................................................... 28
Figure 14.One-Line Mode #1 Serial Audio Format ................................................................................... 29
Figure 15.One-Line Mode #2 Serial Audio Format ................................................................................... 29
Figure 16.ADCIN1/ADCIN2 Serial Audio Format ...................................................................................... 30
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CS42426
Figure 17.OLM Configuration #1 ............................................................................................................... 31
Figure 18.OLM Configuration #2 ............................................................................................................... 32
Figure 19.OLM Configuration #3 ............................................................................................................... 33
Figure 20.OLM Configuration #4 ............................................................................................................... 34
Figure 21.Control Port Timing in SPI Mode .............................................................................................. 35
Figure 22.Control Port Timing, I²C Write ................................................................................................... 36
Figure 23.Control Port Timing, I²C Read ................................................................................................... 36
Figure 24.Recommended Analog Input Buffer .......................................................................................... 61
Figure 25.Recommended Analog Output Buffer ....................................................................................... 61
Figure 26.Recommended Layout Example ............................................................................................... 63
Figure 27.Single-Speed Mode Stopband Rejection .................................................................................. 64
Figure 28.Single-Speed Mode Transition Band ........................................................................................ 64
Figure 29.Single-Speed Mode Transition Band (Detail) ............................................................................ 64
Figure 30.Single-Speed Mode Passband Ripple ...................................................................................... 64
Figure 31.Double-Speed Mode Stopband Rejection ................................................................................. 64
Figure 32.Double-Speed Mode Transition Band ....................................................................................... 64
Figure 33.Double-Speed Mode Transition Band (Detail) .......................................................................... 65
Figure 34.Double-Speed Mode Passband Ripple ..................................................................................... 65
Figure 35.Quad-Speed Mode Stopband Rejection ................................................................................... 65
Figure 36.Quad-Speed Mode Transition Band ......................................................................................... 65
Figure 37.Quad-Speed Mode Transition Band (Detail) ............................................................................. 65
Figure 38.Quad-Speed Mode Passband Ripple ....................................................................................... 65
Figure 39.Single-Speed (fast) Stopband Rejection ................................................................................... 66
Figure 40.Single-Speed (fast) Transition Band ......................................................................................... 66
Figure 41.Single-Speed (fast) Transition Band (detail) ............................................................................. 66
Figure 42.Single-Speed (fast) Passband Ripple ....................................................................................... 66
Figure 43.Single-Speed (slow) Stopband Rejection ................................................................................. 66
Figure 44.Single-Speed (slow) Transition Band ........................................................................................ 66
Figure 45.Single-Speed (slow) Transition Band (detail) ............................................................................ 67
Figure 46.Single-Speed (slow) Passband Ripple ...................................................................................... 67
Figure 47.Double-Speed (fast) Stopband Rejection ................................................................................. 67
Figure 48.Double-Speed (fast) Transition Band ........................................................................................ 67
Figure 49.Double-Speed (fast) Transition Band (detail) ............................................................................ 67
Figure 50.Double-Speed (fast) Passband Ripple ...................................................................................... 67
Figure 51.Double-Speed (slow) Stopband Rejection ................................................................................ 68
Figure 52.Double-Speed (slow) Transition Band ...................................................................................... 68
Figure 53.Double-Speed (slow) Transition Band (detail) .......................................................................... 68
Figure 54.Double-Speed (slow) Passband Ripple .................................................................................... 68
Figure 55.Quad-Speed (fast) Stopband Rejection .................................................................................... 68
Figure 56.Quad-Speed (fast) Transition Band .......................................................................................... 68
Figure 57.Quad-Speed (fast) Transition Band (detail) .............................................................................. 69
Figure 58.Quad-Speed (fast) Passband Ripple ........................................................................................ 69
Figure 59.Quad-Speed (slow) Stopband Rejection ................................................................................... 69
Figure 60.Quad-Speed (slow) Transition Band ......................................................................................... 69
Figure 61.Quad-Speed (slow) Transition Band (detail) ............................................................................. 69
Figure 62.Quad-Speed (slow) Passband Ripple ....................................................................................... 69
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LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 24
Table 2. Common PLL Output Clock Frequencies..................................................................................... 24
Table 3. Slave Mode Clock Ratios ............................................................................................................. 25
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26
Table 5. DAC De-Emphasis ....................................................................................................................... 44
Table 6. Digital Interface Formats .............................................................................................................. 45
Table 7. ADC One-Line Mode.................................................................................................................... 45
Table 8. DAC One-Line Mode.................................................................................................................... 45
Table 9. RMCK Divider Settings ................................................................................................................ 48
Table 10. OMCK Frequency Settings ........................................................................................................ 48
Table 11. Master Clock Source Select....................................................................................................... 49
Table 12. PLL Clock Frequency Detection................................................................................................. 50
Table 13. Example Digital Volume Settings ............................................................................................... 53
Table 14. ATAPI Decode ........................................................................................................................... 54
Table 15. Example ADC Input Gain Settings ............................................................................................. 55
Table 16. PLL External Component Values ............................................................................................... 62
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