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CS42448
108 dB, 192 kHz 6-In, 8-Out CODEC
FEATURES
GENERAL DESCRIPTION
 Six 24-bit A/D, Eight 24-bit D/A Converters
 ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
 DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
 ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
 Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
 System Sampling Rates up to 192 kHz
 Programmable ADC High-Pass Filter for DC
Offset Calibration
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
Logarithmic Digital Volume Control
 I²C® & SPIHost Control Port
 Supports Logic Levels Between 5 V and 1.8 V
 Popguard® Technology
The CS42448 CODEC provides six multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of operation with ei-
ther differential or single-ended inputs and outputs, in a
64-pin LQFP package.
Six fully differential, or single-ended, inputs are avail-
able on stereo ADC1, ADC2, and ADC3. When
operating in Single-ended Mode, an internal MUX be-
fore ADC3 allows selection from up to four single-ended
inputs. Digital volume control is provided for each ADC
channel, with selectable overflow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42448 is available in a 64-pin LQFP package in
Commercial (-10° to +70°) and Automotive (-40° to
+105°) grades. The CDB42448 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 64 for complete ordering
information.
The CS42448 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Digital Supply =
3.3 V to 5 V
Analog Supply =
3.3 V to 5 V
I2C/SPI
Software Mode
Control Data
Interrupt
Reset
Register
Configuration
ADC Overflow
& Clock Error
Interrupt
Internal Voltage
Reference
External
Mute Control
Mute
Control
Serial Audio
Input
Auxilliary Serial
Audio Input
Input Master
Clock
Serial Audio
Output
http://www.cirrus.com
Volume
Controls
Digital
Filters
ΔΣ
Modulators
Multibit
DAC1-4 and
8
Differential or
Single-Ended
Analog Filters
Outputs
8
High Pass
Filter
High Pass
Filter
Digital
Filters
Digital
Filters
Multibit
Oversampling
ADC1&2
Multibit
Oversampling
ADC3
4
4
2
2
*Optional MUX allows selection from up to 4 single-ended inputs.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
Differential or
Single-Ended
Analog Inputs
NOVEMBER '06
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CS42448
TABLE OF CONTENTS
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1. PIN DESCRIPTIONS
.................................................................................................................... 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAM
............................................................................................. 9
3. CHARACTERISTICS AND SPECIFICATIONS..................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ................................................................................... 10
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 10
ANALOG INPUT CHARACTERISTICS (COMMERCIAL) .................................................................... 11
ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) ..................................................................... 12
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 13
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) ................................................................ 14
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) ................................................................. 15
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 17
SWITCHING SPECIFICATIONS - ADC/DAC PORT ............................................................................ 18
SWITCHING CHARACTERISTICS - AUX PORT ................................................................................. 20
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE ....................................................... 21
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................................. 22
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 23
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 23
4. APPLICATIONS .................................................................................................................................... 24
4.1 Overview ......................................................................................................................................... 24
4.2 Analog Inputs .................................................................................................................................. 24
4.2.1 Line-Level Inputs ................................................................................................................... 24
4.2.2 ADC3 Analog Input ................................................................................................................ 25
4.2.3 High-Pass Filter and DC Offset Calibration ........................................................................... 26
4.3 Analog Outputs ............................................................................................................................... 26
4.3.1 Initialization ............................................................................................................................ 26
4.3.2 Output Transient Control ....................................................................................................... 28
4.3.3 Popguard ............................................................................................................................... 28
4.3.3.1 Power-Up ................................................................................................................... 28
4.3.3.2 Power-Down .............................................................................................................. 28
4.3.4 Mute Control .......................................................................................................................... 28
4.3.5 Line-Level Outputs and Filtering ............................................................................................ 29
4.3.6 Digital Volume Control ........................................................................................................... 29
4.3.7 De-Emphasis Filter ................................................................................................................ 29
4.4 System Clocking ............................................................................................................................. 30
4.5 CODEC Digital Interface Formats ................................................................................................... 31
4.5.1 I²S .......................................................................................................................................... 32
4.5.2 Left-Justified .......................................................................................................................... 32
4.5.3 Right-Justified ........................................................................................................................ 32
4.5.4 OLM #1 .................................................................................................................................. 32
4.5.5 OLM #2 .................................................................................................................................. 33
4.5.6 TDM ....................................................................................................................................... 33
4.5.7 I/O Channel Allocation ........................................................................................................... 34
4.6 AUX Port Digital Interface Formats ................................................................................................. 34
4.6.1 I²S .......................................................................................................................................... 34
4.6.2 Left-Justified .......................................................................................................................... 34
4.7 Control Port Description and Timing ............................................................................................... 35
4.7.1 SPI Mode ............................................................................................................................... 35
4.7.2 I²C Mode ................................................................................................................................ 36
4.8 Interrupts ......................................................................................................................................... 37
4.9 Recommended Power-Up Sequence ............................................................................................. 37
4.10 Reset and Power-Up .................................................................................................................... 38
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CS42448
4.11 Power Supply, Grounding, and PCB Layout ................................................................................. 38
5. REGISTER QUICK REFERENCE ......................................................................................................... 39
6. REGISTER DESCRIPTION ................................................................................................................... 41
6.1 Memory Address Pointer (MAP) ..................................................................................................... 41
6.1.1 Increment (INCR) .................................................................................................................. 41
6.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 41
6.2 Chip I.D. and Revision Register (Address 01h) (Read Only) .......................................................... 41
6.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 41
6.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 41
6.3 Power Control (Address 02h) ......................................................................................................... 42
6.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 42
6.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 42
6.3.3 Power Down (PDN) ............................................................................................................... 42
6.4 Functional Mode (Address 03h) ...................................................................................................... 43
6.4.1 DAC Functional Mode (DAC_FM[1:0]) .................................................................................. 43
6.4.2 ADC Functional Mode (ADC_FM[1:0]) .................................................................................. 43
6.4.3 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 43
6.5 Interface Formats (Address 04h) .................................................................................................... 44
6.5.1 Freeze Controls (FREEZE) ................................................................................................... 44
6.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 44
6.5.3 DAC Digital Interface Format (DAC_DIF[2:0]) ....................................................................... 44
6.5.4 ADC Digital Interface Format (ADC_DIF[2:0]) ....................................................................... 45
6.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 45
6.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 45
6.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) ......................................................... 46
6.6.3 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 46
6.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 46
6.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 46
6.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) ......................................................................... 47
6.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) ......................................................................... 47
6.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) ......................................................................... 47
6.7 Transition Control (Address 06h) .................................................................................................... 47
6.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 47
6.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 48
6.7.3 Auto-Mute (AMUTE) .............................................................................................................. 48
6.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 49
6.8 DAC Channel Mute (Address 07h) ................................................................................................. 49
6.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 49
6.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 49
6.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 49
6.10 DAC Channel Invert (Address 10h) .............................................................................................. 50
6.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 50
6.11 AINX Volume Control (Address 11h-16h) ..................................................................................... 50
6.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 50
6.12 ADC Channel Invert (Address 17h) .............................................................................................. 50
6.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 50
6.13 When enabled, these bits will invert the signal polarity of their respective channels.Status Control
(Address 18h) ....................................................................................................................................... 51
6.13.1 Interrupt Pin Control (INT[1:0]) ............................................................................................ 51
6.14 Status (Address 19h) (Read Only) ................................................................................................ 51
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) ........................................................................ 51
6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) ........................................................................ 51
6.14.3 ADC Overflow (ADCX_OVFL) ............................................................................................. 51
6.15 Status Mask (Address 1Ah) .......................................................................................................... 52
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6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 52
6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 52
6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE) ............................................................................. 52
7. EXTERNAL FILTERS............................................................................................................................ 53
7.1 ADC Input Filter .............................................................................................................................. 53
7.1.1 Passive Input Filter ................................................................................................................ 54
7.1.2 Passive Input Filter w/Attenuation ......................................................................................... 54
7.2 DAC Output Filter ........................................................................................................................... 56
8. ADC FILTER PLOTS............................................................................................................................. 57
9. DAC FILTER PLOTS............................................................................................................................. 59
10. PARAMETER DEFINITIONS............................................................................................................... 61
11. REFERENCES..................................................................................................................................... 62
12. PACKAGE INFORMATION................................................................................................................. 63
12.1 Thermal Characteristics ............................................................................................................... 63
13. ORDERING INFORMATION ............................................................................................................... 64
14. REVISION HISTORY ........................................................................................................................... 64
LIST OF FIGURES
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Figure 1.Typical Connection Diagram ......................................................................................................... 9
Figure 2.Output Test Circuit for Maximum Load ....................................................................................... 16
Figure 3.Maximum Loading ....................................................................................................................... 16
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 18
Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 18
Figure 6.Serial Audio Interface Master Mode Timing ................................................................................ 19
Figure 7.Serial Audio Interface Slave Mode Timing .................................................................................. 20
Figure 8.Control Port Timing - I²C Format ................................................................................................. 21
Figure 9.Control Port Timing - SPI Format ................................................................................................ 22
Figure 10.Full-Scale Input ......................................................................................................................... 25
Figure 11.ADC3 Input Topology ................................................................................................................ 25
Figure 12.Audio Output Initialization Flow Chart ....................................................................................... 27
Figure 13.Full-Scale Output ...................................................................................................................... 29
Figure 14.De-Emphasis Curve .................................................................................................................. 30
Figure 15.I²S Format ................................................................................................................................. 32
Figure 16.Left Justified Format ................................................................................................................. 32
Figure 17.Right Justified Format ............................................................................................................... 32
Figure 18.One-Line Mode #1 Format ........................................................................................................ 32
Figure 19.One Line Mode #2 Format ........................................................................................................ 33
Figure 20.TDM Format .............................................................................................................................. 33
Figure 21.AUX I²S Format ......................................................................................................................... 34
Figure 22.AUX Left-Justified Format ......................................................................................................... 35
Figure 23.Control Port Timing in SPI Mode .............................................................................................. 36
Figure 24.Control Port Timing, I²C Write ................................................................................................... 36
Figure 25.Control Port Timing, I²C Read ................................................................................................... 37
Figure 26.Single to Differential Active Input Filter ..................................................................................... 53
Figure 27.Single-Ended Active Input Filter ................................................................................................ 53
Figure 28.Passive Input Filter ................................................................................................................... 54
Figure 29.Passive Input Filter w/Attenuation ............................................................................................. 55
Figure 30.Active Analog Output Filter ....................................................................................................... 56
Figure 31.Passive Analog Output Filter .................................................................................................... 56
Figure 32.SSM Stopband Rejection .......................................................................................................... 57
Figure 33.SSM Transition Band ................................................................................................................ 57
Figure 34.SSM Transition Band (Detail) ................................................................................................... 57
Figure 35.SSM Passband Ripple .............................................................................................................. 57
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Figure 36.DSM Stopband Rejection .......................................................................................................... 57
Figure 37.DSM Transition Band ................................................................................................................ 57
Figure 38.DSM Transition Band (Detail) ................................................................................................... 58
Figure 39.DSM Passband Ripple .............................................................................................................. 58
Figure 40.QSM Stopband Rejection ......................................................................................................... 58
Figure 41.QSM Transition Band ................................................................................................................ 58
Figure 42.QSM Transition Band (Detail) ................................................................................................... 58
Figure 43.QSM Passband Ripple .............................................................................................................. 58
Figure 44.SSM Stopband Rejection .......................................................................................................... 59
Figure 45.SSM Transition Band ................................................................................................................ 59
Figure 46.SSM Transition Band (detail) .................................................................................................... 59
Figure 47.SSM Passband Ripple .............................................................................................................. 59
Figure 48.DSM Stopband Rejection .......................................................................................................... 59
Figure 49.DSM Transition Band ................................................................................................................ 59
Figure 50.DSM Transition Band (detail) .................................................................................................... 60
Figure 51.DSM Passband Ripple .............................................................................................................. 60
Figure 52.QSM Stopband Rejection ......................................................................................................... 60
Figure 53.QSM Transition Band ................................................................................................................ 60
Figure 54.QSM Transition Band (detail) .................................................................................................... 60
Figure 55.QSM Passband Ripple .............................................................................................................. 60
LIST OF TABLES
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Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Single-Speed Mode Common Frequencies ................................................................................ 30
Table 3. Double-Speed Mode Common Frequencies ............................................................................... 30
Table 4. Quad-Speed Mode Common Frequencies ................................................................................. 30
Table 5. I²S, LJ, RJ Clock Ratios .............................................................................................................. 31
Table 6. OLM#1 Clock Ratios ................................................................................................................... 31
Table 7. OLM#2 Clock Ratios ................................................................................................................... 31
Table 8. TDM Clock Ratios ....................................................................................................................... 31
Table 9. Serial Audio Interface Channel Allocations ................................................................................. 34
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats .......................... 43
Table 12. DAC Digital Interface Formats .................................................................................................. 44
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats ................................................. 44
Table 13. ADC Digital Interface Formats .................................................................................................. 45
Table 14. Example AOUT Volume Settings .............................................................................................. 49
Table 15. Example AIN Volume Settings .................................................................................................. 50
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