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FEATURES
6-Phase Vertical Transfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 27 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 800 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
10-Bit CCD Signal Processor with
Precision Timing Generator
AD9991
GENERAL DESCRIPTION
The AD9991 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with 800 ps resolution at 27 MHz operation.
The AD9991 is specified at pixel rates of up to 27 MHz. The
analog front end includes black level clamping, CDS, VGA,
and a 10-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9991 is speci-
fied over an operating temperature range of –20°C to +85°C.
www.DataSheet4U.com
CCDIN
RG
H1–H4
V1–V6
VSG1–VSG5
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
CDS
6dB TO 42dB
VGA
VREF
AD9991
10-BIT
ADC
10
INTERNAL CLOCKS
CLAMP
HORIZONTAL
4 DRIVERS
6
V-H
5 CONTROL
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DOUT
DCLK
MSHUT
STROBE
VSUB SUBCK
HD VD SYNC CLI CLO SL SCK DATA
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.

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AD9991
TABLE OF CONTENTS
SPECIFICATIONS ............................................................... 3
Digital Specifications .......................................................... 3
Analog Specifications ........................................................... 4
Timing Specifications........................................................... 5
ABSOLUTE MAXIMUM RATINGS ..................................... 5
PACKAGE THERMAL CHARACTERISTICS ...................... 5
ORDERING GUIDE ............................................................. 5
PIN CONFIGURATION ....................................................... 6
PIN FUNCTION DESCRIPTIONS....................................... 6
TERMINOLOGY .................................................................. 7
EQUIVALENT CIRCUITS.................................................... 7
TYPICAL PERFORMANCE CHARACTERISTICS ............. 8
SYSTEM OVERVIEW............................................................ 9
PRECISION TIMING HIGH SPEED TIMING
GENERATION .................................................................... 10
Timing Resolution ............................................................. 10
High Speed Clock Programmability.................................... 10
H-Driver and RG Outputs ................................................. 11
Digital Data Outputs ........................................................ 11
HORIZONTAL CLAMPING AND BLANKING ................. 13
Individual CLPOB and PBLK Patterns .............................. 13
Individual HBLK Patterns ................................................. 13
Generating Special HBLK Patterns .................................... 14
Generating HBLK Line Alteration ..................................... 14
HORIZONTAL TIMING SEQUENCE EXAMPLE ............. 15
VERTICAL TIMING GENERATION ................................. 16
Vertical Pattern Groups ...................................................... 17
Vertical Sequences.............................................................. 18
Complete Field: Combining V-Sequences ........................... 19
Generating Line Alternation for V-Sequence and HBLK...... 20
Second V-Pattern Group during VSG Active Line................ 20
Sweep Mode Operation...................................................... 21
Multiplier Mode ................................................................ 21
Vertical Sensor Gate (Shift Gate) Patterns........................... 22
MODE Register ................................................................ 23
VERTICAL TIMING EXAMPLE ....................................... 24
Important Note about Signal Polarities ............................... 24
SHUTTER TIMING CONTROL ........................................ 26
Normal Shutter Operation ................................................. 26
High Precision Shutter Operation....................................... 26
Low Speed Shutter Operation ............................................ 26
SUBCK Suppression ......................................................... 27
Readout after Exposure...................................................... 27
Using the TRIGGER Register ............................................ 27
VSUB Control ................................................................... 28
MSHUT and STROBE Control ........................................ 28
TRIGGER Register Limitations ......................................... 29
EXPOSURE AND READOUT EXAMPLE.......................... 30
ANALOG FRONT END DESCRIPTION
AND OPERATION ......................................................... 31
DC Restore ..................................................................... 31
Correlated Double Sampler............................................... 31
Variable Gain Amplifier .................................................... 31
A/D Converter .................................................................. 31
Optical Black Clamp......................................................... 32
Digital Data Outputs ......................................................... 32
POWER-UP AND SYNCHRONIZATION........................... 33
Recommended Power-Up Sequence for Master Mode......... 33
Generating Software SYNC without
External SYNC Signal ................................................... 33
SYNC during Master Mode Operation............................... 34
Power-Up and Synchronization in Slave Mode.................... 34
STANDBY MODE OPERATION ........................................ 34
CIRCUIT LAYOUT INFORMATION................................. 36
SERIAL INTERFACE TIMING........................................... 37
Register Address Banks 1 and 2.......................................... 38
Updating of New Register Values........................................ 39
COMPLETE LISTING OF REGISTER BANK 1 ............... 40
COMPLETE LISTING OF REGISTER BANK 2 ............... 43
OUTLINE DIMENSIONS.................................................. 59
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AD9991–SPECIFICATIONS
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1–H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
POWER DISSIPATION (See TPC 1 for Power Curves)
27 MHz, Typ Supply Levels, 100 pF H1–H4 Loading
Power from HVDD Only*
Standby 1 Mode
Standby 2 Mode
Standby 3 Mode
MAXIMUM CLOCK RATE (CLI)
Min Typ
–20
–65
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
2.7 3.0
270
100
105
10
0.5
27
*The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power = [CLOAD ϫ HVDD ϫ Pixel Frequency] ϫ HVDD ϫ Number of H-outputs used
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
Unit
°C
°C
V
V
V
V
V
V
mW
mW
mW
mW
mW
MHz
DIGITAL SPECIFICATIONS (RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.)
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ IOH = 2 mA
Low Level Output Voltage @ IOL = 2 mA
RG and H-DRIVER OUTPUTS (H1–H4)
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
Maximum Output Current (Programmable)
Maximum Load Capacitance (For Each Output)
Symbol
VIH
VIL
IIH
IIL
CIN
VOH
VOL
VOH
VOL
Min Typ
2.1
10
10
10
2.2
VDD – 0.5
30
100
Max Unit
V
0.6 V
µA
µA
pF
V
0.5 V
V
0.5 V
mA
pF
Specifications subject to change without notice.
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AD9991
ANALOG SPECIFICATIONS (AVDD = 3.0 V, fCLI = 27 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)
Parameter
Min Typ
Max
Unit
Notes
CDS*
Allowable CCD Reset Transient
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
1.0
500
±50
mV
V p-p
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Code 0)
Max Gain (VGA Code 1023)
1024
Guaranteed
6
42
Steps
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level (Code 0)
Max Clamp Level (Code 255)
256
0
63.75
Steps
LSB
LSB
Measured at ADC output.
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
10 Bits
–1.0 ±0.5 +1.0 LSB
Guaranteed
2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
2.0 V
1.0 V
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 0)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
5.0
40.5
5.5
41.5
0.2
0.25
50
Includes entire signal chain.
6.0 dB
Gain = (0.0351 ϫ Code) + 6 dB
42.5 dB
% 12 dB gain applied.
LSB rms AC grounded input, 6 dB gain applied.
dB Measured with step change on supply.
500mV TYP
RESET TRANSIENT
50mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
Specifications subject to change without notice.
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AD9991
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 27 MHz, unless otherwise noted.)
Parameter
Symbol
Min Typ Max
MASTER CLOCK, CLI (Figure 4)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLPOB Pulsewidth1, 2 (Figures 9 and 14)
AFE SAMPLE LOCATION1 (Figure 7)
SHP Sample Edge to SHD Sample Edge
DATA OUTPUTS (Figures 8a and 8b)
Output Delay from DCLK Rising Edge1
Pipeline Delay from SHP/SHD Sampling to DOUT
tCONV
tCLIDLY
tS1
tOD
37
14.8 18.5 21.8
6
2 20
17 18.5
8
11
SERIAL INTERFACE (Figures 40a and 40b)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
To Min Max
Unit
AVDD
AVSS –0.3 +3.9
V
TCVDD
TCVSS –0.3 +3.9
V
HVDD
HVSS –0.3 +3.9
V
RGVDD
RGVSS –0.3 +3.9
V
DVDD
DVSS –0.3 +3.9
V
DRVDD
DRVSS –0.3 +3.9
V
RG Output
RGVSS –0.3 RGVDD + 0.3 V
H1–H4 Output
HVSS –0.3 HVDD + 0.3 V
Digital Outputs
DVSS –0.3 DVDD + 0.3 V
Digital Inputs
DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA
DVSS –0.3 DVDD + 0.3 V
REFT, REFB, CCDIN AVSS
–0.3 AVDD + 0.3 V
Junction Temperature
150 °C
Lead Temperature, 10 sec
350 °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA = 25°C/W*
*JA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
AD9991KCP –20°C to +85°C LFCSP
AD9991KCPRL –20°C to +85°C LFCSP
Package
Option
CP-56
CP-56
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9991 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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