ARIZONA MICROTEK, INC.
ECL/PECL 1:9 Differential Clock Driver
• Operating Range of 3.0V to 5.5V
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• 75kΩ Internal Pulldown Resistors
• Direct Replacement for ON
PLCC 28 RoHS
Compliant / Lead
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The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs.
The AZ100LVE111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/I¯N¯
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the VBB pin should be
bypassed to ground via a 0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
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