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ARIZONA MICROTEK, INC.
AZ100LVE310
ECL/PECL 2:8 Differential Clock Driver
FEATURES
PACKAGE AVAILABILITY
Operating Range of 3.0V to 5.5V
Low Skew
PACKAGE PART NUMBER MARKING NOTES
Guaranteed Skew Spec
Differential Design
VBB Output
75kΩ Internal Input Pulldown Resistors
PLCC 28
AZ100LVE310FN
AZM100LVE310
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
Direct Replacement for ON Semiconductor
MC100LVE310 & MC100E310
DESCRIPTION
The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE310 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB pin should be used only
as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the VBB pin should be
bypassed to ground via a 0.01μF capacitor.
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
Q0 Q0 Q1 VCCO Q1 Q2 Q2
25 24 23 22 21 20 19
VEE 26
18 Q3
CLK_SEL 27
17 Q3
CLKa 28
VCC 1
CLKa
2
Pinout: 28-Lead
PLCC (top view)
16 Q4
15 VCCO
14 Q4
VBB 3
13 Q5
CLKb
4
56
CLKb NC
12 Q5
7 8 9 10 11
Q7 VCCO
Q7
Q6
Q6
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
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AZ100LVE310
PIN DESCRIPTION
PIN
CLKa, C¯¯L¯K¯a¯
CLKb, C¯¯L¯K¯b¯
CLK_SEL
Q0, Q¯¯0 – Q7, Q¯¯7
VBB
VCC , VCCO
VEE
NC
FUNCTION
Differential Input Pairs
Differential Input Pairs
Input Clock Select
Differential Output Pairs
VBB Output
Positive Supply
Negative Supply
No Connect
CLK_SEL
0
1
Input Clock
CLKa Selected
CLKb Selected
CLKa
CLKa
CLKb
CLKb
CLK_SEL
LOGIC SYMBOL
VBB
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
IOUT
Output Current
--- Continuous
--- Surge
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1 -1085 -1005 -880 -1025 -955 -880 -1025
VOL Output LOW Voltage1 -1830 -1695 -1555 -1810 -1705 -1620 -1810
VIH
Input HIGH Voltage
-1165
-880 -1165
-880 -1165
VIL
Input LOW Voltage
-1810
-1475 -1810
-1475 -1810
VBB
Reference Voltage
-1380
-1260 -1380
-1260 -1380
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
55 60
55 60
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
-955
-1705
55
Max
-880
-1620
-880
-1475
-1260
150
60
Min
-1025
-1810
-1165
-1810
-1380
0.5
85°C
Typ
-955
-1705
65
Max
-880
-1620
-880
-1475
-1260
150
70
Unit
mV
mV
mV
mV
mV
μA
μA
mA
November 2006 * REV - 4
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AZ100LVE310
100K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 2215 2295 2420 2275 2345 2420 2275
VOL
Output LOW Voltage1,2
1470 1605 1745 1490 1595 1680 1490
VIH
Input HIGH Voltage1
2135
2420 2135
2420 2135
VIL Input LOW Voltage1 1490
1825 1490
1825 1490
VBB Reference Voltage1
1920
2040 1920
2040 1920
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
55 60
55 60
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
100K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 3915 3995 4120 3975 4045 4120 3975
VOL
Output LOW Voltage1,2
3170 3305 3445 3190 3295 3380 3190
VIH
Input HIGH Voltage1
3835
4120 3835
4120 3835
VIL Input LOW Voltage1 3190
3525 3190
3525 3190
VBB Reference Voltage1
3620
3740 3620
3740 3620
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
55 60
55 60
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
2345
1595
Max
2420
1680
2420
1825
2040
150
55 60
25°C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
55 60
Min
2275
1490
2135
1490
1920
0.5
Min
3975
3190
3835
3190
3620
0.5
85°C
Typ
2345
1595
65
85°C
Typ
4045
3295
65
Max
2420
1680
2420
1825
2040
150
70
Max
4120
3380
4120
3525
3740
150
70
Unit
mV
mV
mV
mV
mV
μA
μA
mA
Unit
mV
mV
mV
mV
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND or VEE = GND, VCC = VCCO = +3.0 to +5.5V)
Symbol
Characteristic
-40°C
0°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tPLH / tPHL
Propagation Delay to
Output
IN (Diff)1
IN (SE)2
525
500
725 550
750 550
750 550
775 550
750 575
800 600
775
850
tSKEW
VPP (AC)
VCMR
Within-Device Skew
Part-to-Part Skew (Diff)3
Minimum Input Swing4
Common Mode Range5
250
VEE +
1.8
75
250
VCC -
0.4
250
VEE +
1.8
75
250
VCC -
0.4
250
VEE +
1.8
50
200
VCC -
0.4
250
VEE +
1.8
50
200
VCC -
0.4
tr / tf
Rise/Fall Time
20 – 80%
250 450 650 275 375 600 275 375 600 275 375 600
1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.
4. VPP is the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the LVE310,
because differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min).
Unit
ps
ps
mV
V
ps
November 2006 * REV - 4
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AZ100LVE310
PACKAGE DIAGRAM
PLCC 28
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
T
Z
G1
K1
MILLIMETERS
MIN MAX
12.32 12.57
12.32 12.57
4.20 4.57
2.29 2.79
0.33 0.48
1.27 BSC
0.66 0.81
0.51
0.64
11.43 11.58
11.43 11.58
1.07 1.21
1.07 1.21
1.07 1.42
0.50
2O 10O
10.42 10.92
1.02
INCHES
MIN MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2O 10O
0.410 0.430
0.040
NOTES:
1. DATUMS –L-, -M-, AND –N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALOWABLE MOLD FLASH IS
0.010mm (0.250in.) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKGE BOTTOM BY UP TO 0.012mm
(0.300in.). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, THE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN
THE TOP AND BOTTOM OF THE PLASTIC
BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE SMALLER THAN 0.025mm
(0.635in.).
November 2006 * REV - 4
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AZ100LVE310
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
November 2006 * REV - 4
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