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ARIZONA MICROTEK, INC.
AZ10LVE111E
AZ100LVE111E
ECL/PECL 1:9 Differential Clock Driver with Enable
FEATURES
PACKAGE AVAILABILITY
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
PACKAGE
PLCC 28
PART NO.
AZ10LVE111EFN
MARKING
AZ10
LVE111E
<Date Code>
NOTES
1,2
Differential Design
AZ100
Enable
PLCC 28
AZ100LVE111EFN LVE111E
1,2
VBB Output
75kΩ Internal Input Pulldown Resistors
<Date Code>
1 Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
Direct Replacement for ON Semiconductor
MC10E111 & MC100E111
DESCRIPTION
The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the
device by forcing all Q outputs LOW and all Q¯ outputs HIGH.
The AZ100LVE111E provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/I¯N¯
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. The VBB pin should be used only as a
bias for the AZ100LVE111E as its current sink/source capability is limited. When used, the VBB pin should be
bypassed to ground via a 0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate within-device skew, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
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AZ10LVE111E
AZ100LVE111E
Q0 Q0
Q1 VCCO
Q1
Q2 Q2
25 24
23 22 21
20 19
VEE 26
18 Q3
EN 27
17 Q3
IN 28
VCC 1
IN 2
Pinout: 28-Lead
PLCC (top view)
16 Q4
15 VCCO
14 Q4
VBB 3
13 Q5
NC 4
12 Q5
5 6 7 8 9 10 11
Q8 Q8 Q7 VCCO Q7
Q6 Q6
PIN DESCRIPTION
PIN
IN, I¯N¯
E¯N¯
Q0, Q¯¯0 - Q8, Q¯¯8
VBB
VCC , VCCO
VEE
NC
FUNCTION
Differential Input Pair
Enable
Differential Outputs
VBB Output
Positive Supply
Negative Supply
No Connect
IN
IN
EN
V BB
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
IOUT
Output Current
--- Continuous
--- Surge
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
10K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max
VOH Output HIGH Voltage1 -1080
VOL Output LOW Voltage1 -1950
-890 -1020
-1650 -1950
-840
-1630
VIH
Input HIGH Voltage
-1230
-890 -1170
-840
VIL
Input LOW Voltage
-1950
-1500 -1950
-1480
VBB
Reference Voltage
-1430
-1300 -1380
-1270
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
Min
-980
-1950
-1130
-1950
-1350
0.5
25°C
Typ
48
Max
-810
-1630
-810
-1480
-1250
150
60
Min
-910
-1950
-1060
-1950
-1310
0.5
85°C
Typ
48
Max
-720
-1595
-720
-1445
-1190
150
60
November 2006 * REV - 4
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2
Unit
mV
mV
mV
mV
mV
μA
μA
mA

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AZ10LVE111E
AZ100LVE111E
10K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 2220
VOL
Output LOW Voltage1,2
1350
VIH
Input HIGH Voltage1
2070
VIL Input LOW Voltage1 1350
VBB Reference Voltage1
1870
2410
1650
2410
1800
2000
2280
1350
2130
1350
1920
2460
1670
2460
1820
2030
2320
1350
2170
1350
1950
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
48
Max
2490
1670
2490
1820
2050
150
60
Min
2390
1350
2240
1350
1990
0.3
85°C
Typ
48
Max
2580
1705
2580
1855
2110
150
60
10K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 3920
VOL
Output LOW Voltage1,2
3050
VIH
Input HIGH Voltage1
3770
VIL Input LOW Voltage1 3050
VBB Reference Voltage1
3570
4110
3350
4110
3500
3700
3980
3050
3830
3050
3620
4160
3370
4160
3520
3730
4020
3050
3870
3050
3650
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
48
Max
4190
3370
4190
3520
3750
150
60
Min
4090
3050
3940
3050
3690
0.3
85°C
Typ
48
Max
4280
3405
4280
3555
3810
150
60
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1 -1085 -1005 -880 -1025 -955 -880 -1025
VOL Output LOW Voltage1 -1830 -1695 -1555 -1810 -1705 -1620 -1810
VIH
Input HIGH Voltage
-1165
-880 -1165
-880 -1165
VIL
Input LOW Voltage
-1810
-1475 -1810
-1475 -1810
VBB
Reference Voltage
-1380
-1260 -1380
-1260 -1380
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
-955
-1705
48
Max
-880
-1620
-880
-1475
-1260
150
60
Min
-1025
-1810
-1165
-1810
-1380
0.5
85°C
Typ
-955
-1705
55
Max
-880
-1620
-880
-1475
-1260
150
69
100K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 2215 2295 2420 2275 2345 2420 2275
VOL
Output LOW Voltage1,2
1470 1605 1745 1490 1595 1680 1490
VIH
Input HIGH Voltage1
2135
2420 2135
2420 2135
VIL Input LOW Voltage1 1490
1825 1490
1825 1490
VBB Reference Voltage1
1920
2040 1920
2040 1920
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
2345
1595
48
Max
2420
1680
2420
1825
2040
150
60
Min
2275
1490
2135
1490
1920
0.5
85°C
Typ
2345
1595
55
Max
2420
1680
2420
1825
2040
150
69
Unit
mV
mV
mV
mV
mV
μA
μA
mA
Unit
mV
mV
mV
mV
mV
μA
μA
mA
Unit
mV
mV
mV
mV
mV
μA
μA
mA
Unit
mV
mV
mV
mV
mV
μA
μA
mA
November 2006 * REV - 4
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AZ10LVE111E
AZ100LVE111E
100K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 3915 3995 4120 3975 4045 4120 3975
VOL
Output LOW Voltage1,2
3170 3305 3445 3190 3295 3380 3190
VIH
Input HIGH Voltage1
3835
4120 3835
4120 3835
VIL Input LOW Voltage1 3190
3525 3190
3525 3190
VBB Reference Voltage1
3620
3740 3620
3740 3620
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
48 60
Min
3975
3190
3835
3190
3620
0.5
85°C
Typ
4045
3295
55
Max
4120
3380
4120
3525
3740
150
69
Unit
mV
mV
mV
mV
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND or VEE = GND, VCC = VCCO = +3.0 to +5.5V)
Symbol
Characteristic
-40°C
0°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tPLH / tPHL
Propagation Delay
to Output IN (Diff)1
IN (SE)2
Enable3
Disable3
380
280
400
400
650 460
700 410
900 450
900 450
560 480
610 430
850 450
850 450
580 510
630 460
850 450
850 450
610
660
850
850
tS
Setup Time E¯N¯ to IN5 250
0
200 0
200 0
200 0
tH Hold Time IN to E¯N¯ 6 50 -200
0 -200
0 -200
0 -200
tR
Release Time E¯N¯ to IN7 350
100
300 100
300 100
300 100
tskew Within-Device Skew4
25 75
25 50
25 50
25 50
VPP (AC) Minimum Input Swing8 250 250 250 250
VCMR
Common Mode Range9
VEE +
1.8
VCC -
0.4
VEE +
1.8
VCC -
0.4
VEE +
1.8
VCC -
0.4
VEE +
1.8
VCC -
0.4
tr / tf Rise/Fall Time
250
650 275
600 275
600 275
600
1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. Enable is defined as the propagation delay from the 50% point of a negative transition on E¯N¯ to the 50% point of a positive transition on Q (or a
negative transition on Q¯ ). Disable is defined as the propagation delay from the 50% point of a positive transition on E¯N¯ to the 50% point of a
negative transition on Q (or a positive transition on Q¯ ).
4. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.
5. The setup time is the minimum time that E¯N¯ must be asserted prior to the next transition of IN/I¯N¯ to prevent an output response greater than
±75mV to that IN/I¯N¯ transition (see Figure 1).
6. The hold time is the minimum time that E¯N¯ must remain asserted after a negative going IN or a positive going I¯N¯ to prevent an output response
greater than ±75 mV to that IN/I¯N¯ transition (see Figure 2).
7. The release time is the minimum time that E¯N¯ must be de-asserted prior to the next IN/I¯N¯ transition to ensure an output response that meets the
specified IN to Q propagation delay and output transition times (see Figure 3).
8. VPP is defined as the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the
LVE111E, because differential input as low as 50 mV will still produce full ECL levels at the output.
9. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to VPP(min).
Unit
ps
ps
ps
ps
ps
mV
V
ps
IN IN IN
IN IN IN
H
EN EN
EN
November 2006 * REV - 4
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AZ10LVE111E
AZ100LVE111E
PACKAGE DIAGRAM
PLCC 28
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
T
Z
G1
K1
MILLIMETERS
MIN MAX
12.32 12.57
12.32 12.57
4.20 4.57
2.29 2.79
0.33 0.48
1.27 BSC
0.66 0.81
0.51
0.64
11.43 11.58
11.43 11.58
1.07 1.21
1.07 1.21
1.07 1.42
0.50
2O 10O
10.42 10.92
1.02
INCHES
MIN MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2O 10O
0.410 0.430
0.040
NOTES:
1. DATUMS –L-, -M-, AND –N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALOWABLE MOLD FLASH IS
0.010mm (0.250in.) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKGE BOTTOM BY UP TO 0.012mm
(0.300in.). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, THE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN
THE TOP AND BOTTOM OF THE PLASTIC
BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE SMALLER THAN 0.025mm
(0.635in.).
November 2006 * REV - 4
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