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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

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7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM
organized as 131072 word by 8-bit which are fabricated using high-
performance triple-polysilicon and double metal CMOS technology.
The use of thin film transistor (TFT) load cells and CMOS periphery
result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M5V108DVP,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).
FEATURES
Type name
M5M5V108DFP,VP,KV-70H
Access
time
(max)
VCC
Power supply current
Active stand-by
(1MHz)
(max)
(max)
70ns 2.7~3.6V 5mA 12µA
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M5V108DFP ············ 32pin 525mil SOP
M5M5V108DVP,RV ············ 32pin 8 X 20 mm2 TSOP
2
M5M5V108DKV,KR ············ 32pin 8 X 13.4 mm TSOP
APPLICATION
Small capacity memory units
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
GND 16
32 VCC
31
A15
ADDRESS
INPUT
S30
2
CHIP SELECT
INPUT
W29
WRITE CONTROL
INPUT
28 A13
27 A8
26 A9
ADDRESS
INPUTS
25 A11
24
OE OUTPUT ENABLE
INPUT
23
A10
ADDRESS
INPUT
S22
1
CHIP SELECT
INPUT
21 DQ8
20 DQ7
19 DQ6
18 DQ5
DATA
INPUTS/
OUTPUTS
17 DQ4
Outline 32P2M-A
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M5V108DVP,KV
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
Outline 32P3H-E(VP), 32P3K-B(KV)
NC : NO CONNECTION
1

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7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V108D series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
FUNCTION TABLE
S1 S2
XL
HX
LH
LH
LH
W OE Mode
DQ
ICC
X X Non selection High-impedance Stand-by
X X Non selection High-impedance Stand-by
LX
Write
Din
Active
HL
Read
Dout
Active
HH
High-impedance Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
When setting S1 at a high level or S2 at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
BLOCK DIAGRAM
A3 9
A2 10
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A15 31
*
17
18
15
14
13
12
11
10
7
131072 WORDS
X 8 BITS
( 512 ROWS
X128 COLUMNS
X 16BLOCKS )
*
21
22
23
25
26
27
28
29
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
DATA
INPUTS/
OUTPUTS
20 DQ7
21 DQ8
ADDRESS
INPUTS
A13 28
A8 27
A9 26
A11 25
4
3
2
1
A4 8
A1 11
A0 12
A10 23
16
19
20
31
CLOCK
GENERATOR
* Pin numbers inside dotted line show those of TSOP
WRITE
5 29 W CONTROL
INPUT
30 22 S1 CHIP
6
30 S2
SELECT
INPUTS
OUTPUT
32 24 OE ENABLE
INPUT
8 32 VCC
24
16
GND
(0V)
2

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ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
Topr Operating temperature
Tstg Storage temperature
* –3.0V in case of AC ( Pulse width 30ns )
7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.3*~4.6
– 0.3*~Vcc + 0.3
(Max 4.6)
0~Vcc
700
0~70
– 65~150
Unit
V
V
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
Min
VIH
VIL
VOH1
VOH2
VOL
II
IO
ICC1
ICC2
ICC3
ICC4
High-level input voltage
Low-level input voltage
High-level output voltage 1 IOH= – 0.5mA
High-level output voltage 2 IOH= – 0.05mA
Low-level output voltage
Input current
Output current in off-state
Active supply current
Active supply current
Stand-by current
Stand-by current
IOL= 2mA
VI=0~Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
1) S2 0.2V
other inputs=0~VCC
2) S1 VCC–0.2V,
S2 VCC–0.2V
other inputs=0~VCC
S1=VIH or S2=VIL,
other inputs=0~VCC
2.0
–0.3*
2.4
Vcc
– 0.5
70ns
1MHz
~25°C
-H ~40°C
~70°C
Limits
Typ Max
Vcc
+ 0.3
0.6
0.4
±1
±1
35
5
1.2
3.6
12
0.33
Unit
V
V
V
V
V
µA
µA
µA
mA
* –3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE (Ta=0~70°C, unless otherwise noted)
Symbol
CI
CO
Parameter
Input capacitance
Output capacitance
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Note 3: Direction for current flowing into an IC is positive (no mark).
4: Typical value is Vcc = 3V, Ta = 25°C
Limits
Min Typ Max
8
10
Unit
pF
pF
3

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7th.July.2000 Ver. 1.1
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
VCC ................................. 2.7~3.6V
Input pulse level ............. VIH=2.2V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ...............VOH=VOL=1.5V
Output loads ................... Fig.1, CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
-70H
Min Max
70
70
70
70
35
25
25
25
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
-70H
Min Max
70
55
0
65
65
65
30
0
0
25
25
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4