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Data Sheet
FEATURES
High dynamic range, dual DAC parts
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits usable outputs
beyond Nyquist frequency
LVDS inputs with dual-port or optional interleaved single-
port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
Dual 12-/14-/16-Bit,
LVDS Interface, 500 MSPS DACs
AD9780/AD9781/AD9783
GENERAL DESCRIPTION
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
The devices include specific features for direct conversion transmit
applications, including gain and offset compensation, and they
interface seamlessly with analog quadrature modulators such as
the ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
CLKP
CLKN
LVDS
INTERFACE
D[15:0]
VIA, VIB
FUNCTIONAL BLOCK DIAGRAM
AD9783 DUAL LVDS DAC
INTERFACE LOGIC
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
16-BIT
I DAC
16-BIT
Q DAC
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.

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AD9780/AD9781/AD9783
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Serial Peripheral Interface ......................................................... 19
REVISION HISTORY
6/12—Rev. A to Rev. B
Changes to Table 2............................................................................ 4
Changes to Pins 25, 26, 29, and 30 Description, Table 6............. 7
Changes to Pins 9 to 24, 31 to 42, 25, 26, 29, and 30 Description,
Table 7 ................................................................................................ 8
Changes to Pins 25, 26, 29, and 30 Description, Table 7............. 9
Changes to SEEK Bit Function Description, Table 12............... 22
Changes to Parallel Data Port Interface Section......................... 25
Changed fDACCLK from 600 MHz to 500 MHz.............................. 26
Added BIST Operation Section .................................................... 27
Changes to Driving the CLK Input Section and Figure 59 ....... 27
Removed Evaluation Board Schematics Section ........................ 31
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
6/08—Rev. 0 to Rev. A
Changed Maximum Sample Rate to 500 MHz Throughout....... 1
Changes to Table 3............................................................................ 4
Changes to Building the Array Section ....................................... 25
Changes to Determining the SMP Value Section....................... 25
Added Evaluation Board Schematics Section............................. 30
Updated Outline Dimensions ....................................................... 35
11/07—Revision 0: Initial Version
Data Sheet
General Operation of the Serial Interface............................... 19
Instruction Byte .......................................................................... 19
MSB/LSB Transfers .................................................................... 20
Serial Interface Port Pin Descriptions ..................................... 20
SPI Register Map ............................................................................ 21
SPI Register Descriptions .............................................................. 22
SPI Port, RESET, and Pin Mode ............................................... 24
Parallel Data Port Interface ........................................................... 25
Optimizing the Parallel Port Timing ....................................... 25
BIST Operation........................................................................... 27
Driving the CLK Input .............................................................. 27
Full-Scale Current Generation ................................................. 28
DAC Transfer Function ............................................................. 28
Analog Modes of Operation ..................................................... 28
Power Dissipation....................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Rev. B | Page 2 of 32

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Data Sheet
AD9780/AD9781/AD9783
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current1
Output Compliance Range
Output Resistance
Main DAC Monotonicity Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
AUX DAC Monotonicity Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
POWER CONSUMPTION
fDAC = 500 MSPS, IF = 20 MHz
fDAC = 500 MSPS, IF = 10 MHz
Power-Down Mode
SUPPLY CURRENTS2
AVDD33
CVDD18
DVDD33
DVDD18
AD9780
Min Typ Max
12
±0.13
±0.25
–0.001
8.66
–1.0
0
±2
20.2
10
+0.001
31.66
+1.0
0.04
100
30
10
–2 +2
0 1.6
0.8 1.6
1
1.2
5
3.13 3.3 3.47
1.70 1.8 1.90
3.13 3.3 3.47
1.70 1.8 1.90
V×I V×I
440
35
55 58
34 38
13 15
68 85
AD9781
Min Typ Max
14
±0.5
±1
–0.001 0
+0.001
±2
8.66 20.2 31.66
–1.0 +1.0
10
0.04
100
30
10
–2 +2
0 1.6
0.8 1.6
1
1.2
5
3.13 3.3 3.47
1.70 1.8 1.90
3.13 3.3 3.47
1.70 1.8 1.90
V×I V×I
440
35
55 58
34 38
13 15
68 85
AD9783
Min Typ Max
16
±2
±4
–0.001 0
+0.001
±2
8.66 20.2 31.66
–1.0 +1.0
10
0.04
100
30
10
–2 +2
0 1.6
0.8 1.6
1
1.2
5
3.13 3.3 3.47
1.70 1.8 1.90
3.13 3.3 3.47
1.70 1.8 1.90
V×I V×I
440
3 35
55 58
34 38
13 15
68 85
Unit
Bits
LSB
LSB
% FSR
% FSR
mA
V
ppm/°C
ppm/°C
ppm/°C
Bits
mA
V
V
V
V
V
V
V
mW
mW
mW
mA
mA
mA
mA
1 Based on a 10 kΩ external resistor.
2 fDAC = 500 MSPS, fOUT = 20 MHz.
Rev. B | Page 3 of 32

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AD9780/AD9781/AD9783
Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
DAC CLOCK INPUT (CLKP, CLKN)
Differential Peak-to-Peak Voltage (CLKP − CLKN)
Common-Mode Voltage
Maximum Clock Rate
DAC CLOCK TO ANALOG OUTPUT DATA LATENCY
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup time, SDI to SCLK (tDS)
Hold Time , SDI to to SCLK (tDH)
Data Valid ,SDO to SCLK, (tDV)
Setup time, CSB to SCLK (tDCSB)
SERIAL PERIPHERAL INTERFACE LOGIC LEVELS
Input Logic High
Input Logic Low
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Input Differential Input Impedance, RIN
Maximum LVDS Input Rate (per DAC)
Min Typ Max
400 800 1600
300 400 500
500
7
40
12.5
12.5
2.0
0.2
2.3
1.4
2.0
0.8
800
−100
80
500
20
1600
+100
120
Unit
mV
mV
MSPS
Cycles
MHz
ns
ns
ns
ns
ns
ns
V
V
mV
mV
mV
Ω
MSPS
Rev. B | Page 4 of 32

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Data Sheet
AD9780/AD9781/AD9783
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 500 MSPS, fOUT = 20 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 500 MSPS, fOUT = 20 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
ONE-TONE NOISE SPECTRAL DENSITY (NSD)
fDAC = 500 MSPS, fOUT = 40 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 20 MHz
fDAC = 491.52 MSPS, fOUT = 80 MHz
fDAC = 491.52 MSPS, fOUT = 411.52 MHz
fDAC = 491.52 MSPS, fOUT = 471.52 MHz
AD9780
AD9781
AD9783
Min Typ
Max Min Typ
Max Min Typ Max Unit
79 78 80 dBc
67 66 68 dBc
55 58 62 dBc
58 62 59 dBc
91 93 86 dBc
80 75 79 dBc
69 70 64 dBc
60.5 61.5 66 dBc
−157
−154.5
−153
−152
−162
−156.5
−153
−152
−165
−157
−154
−153
dBc
dBc
dBc
dBc
−81
−82.5
−82 dBc
−80
−82.5
−81 dBc
−71 −68 −69 dBc
−69 −69 −70 dBc
Rev. B | Page 5 of 32