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The NS16550A UART
Design and Application
Considerations
National Semiconductor
Application Note 491
Martin S Michael
Daniel G Durich
July 1987
BACKGROUND
UARTs like other system components have evolved for
many years to become faster more integrated and less ex-
pensive The rise in popularity of the personal computer with
its focus and competition primarily centered on an architec-
ture introduced by IBM has driven both UART perform-
ance and software compatibility issues As transmission
rates have increased the amount of time the CPU has for
other tasks while handling an active serial channel has been
sharply reduced One byte of data received at 1200 baud
(8 3 ms) is received in th the time at 19 2 kbaud (520 ms)
Software compatibility among the PC-based UARTs is crit-
ical due to the thousands of existing programs which use
the serial channel and the new programs continually being
offered
Higher baud rates and compatibility requirements influence
new UART designs These two constraints result in UARTs
that are capable of higher data rates increasingly indepen-
dent of CPU intervention and providing more autonomous
features while maintaining software compatibility These
development paths have been brought together in a new
UART from National Semiconductor designated the
NS16550A
The NS16550A has all of the registers of its two predeces-
sor parts (INS8250 and NS16450) so it can run all existing
IBM PC XT AT RT and compatible serial port software In
addition it has a programmable mode which incorporates
new high-performance features Of course all of these ad-
vanced features are useful in any asynchronous serial com-
munications application regardless of the host architecture
The reader is assumed to be familiar with the standard fea-
tures of the NS16450 so this paper will concentrate mainly
on the new features of the NS16550A If the reader is unfa-
miliar with these UARTs it is advisable to start by reading
their data sheets
The first section reviews some of the design considerations
and the operation of the NS16550A advanced features The
second section shows an NS16550A initialization routine
written in 80286 assembly code with an explanation of the
routine The third section gives a detailed example of com-
munications drivers written to interface two NS16550As on
individual boards These drivers are written for use with Na-
tional Semiconductor’s DB32032 evaluation boards but can
be ported to any NS32032-based system containing an
NS32202 (ICU)
1 0 Design Considerations and
Operation of the New
UART Features
In order to optimize CPU UART data transactions the
UART design takes into consideration the following con-
straints
GNXTM is a trademark of National Semiconductor Corporation
IBM is a registered trademark of International Business Machines Corporation
VAXTM is a trademark of Digital Equipment Corporation
80286TM is a trademark of Intel Corporation
1 The CPU is usually much faster than the UART at trans-
ferring data A high speed CPU could transfer a byte of
data to from the UART in a minimum of 280 ns The
UART would take over 1800 times longer to transmit re-
ceive this data serially if it were operating at 19 2 kbaud
2 There is a finite amount of wasted CPU time due to
software overhead when stopping its current task to
service the UART (context switching overhead)
3 The CPU may be required to complete a certain portion
of its current task in a multitasking system before servic-
ing the UART This delay is the CPU latency time asso-
ciated with servicing the interrupt The amount of time
that the receiver can accept continuous data after it re-
quests service from the CPU constrains CPU latency
time
The design constraints listed above are met by adding two
FIFOs and specialized transmitter receiver support circuitry
to the existing NS16450 design The FIFOs are 16 bytes
deep one holds data for the transmitter the other for the
receiver (see Figure 1 ) Similarity between the FIFOs stops
with their size as each has been customized for special
FIGURE 1 Rx and Tx FIFOs
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transmitter or receiver functions Each has support circuitry
to minimize software overhead when handling interrupts
The NS16550A receiver optimizes the CPU UART data
transaction via the following features
1 The depth of the Receiver (Rx) FIFO ensures that as
many as 16 characters will be ready to transfer when
the CPU services the Rx interrupt Therefore the CPU
transfer rate is effectively buffered from the serial data
rate
2 The program can select the number of bytes required in
the Rx FIFO (1 4 8 or 14) before the UART issues an
interrupt This allows the software to modify the interrupt
trigger levels depending on its current task or loading It
also ensures that the CPU doesn’t continually waste
time switching context for only a few characters
C1995 National Semiconductor Corporation TL C 9313
RRD-B30M105 Printed in U S A

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3 The Rx FIFO will hold 16 bytes regardless of which trig-
ger level the CPU selects This makes allowances for a
variety of CPU latency times as the FIFO continues to
fill after the interrupt is issued
The NS16550A transmitter optimizes the CPU UART data
transaction via the following features
1 The depth of the Transmitter (Tx) FIFO ensures that as
many as 16 characters can be transferred when the
CPU services the Tx interrupt Once again this effec-
tively buffers the CPU transfer rate from the serial data
rate
2 The Transmitter (Tx) FIFO is similar in structure to
FIFOs the user may have previously set up in RAM The
Tx depth allows the CPU to load 16 characters each
time it switches context to the service routine This re-
duces the impact of the CPU time lost in context switch-
ing
3 Since a time lag in servicing an asynchronous transmit-
ter usually has no penalty CPU latency time is of no
concern to transmitter operation
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through SOUT
as soon as the CPU loads a byte into the Tx FIFO The
UART will prevent loads to the Tx FIFO if it currently holds
16 characters Loading to the Tx FIFO will again be enabled
as soon as the next character is transferred to the Tx shift
register These capabilities account for the largely autono-
mous operation of the Tx
The UART starts the above operations typically with a Tx
interrupt The NS16550A issues a Tx interrupt whenever the
Tx FIFO is empty and the Tx interrupt is enabled except in
the following instance Assume that the Tx FIFO is empty
and the CPU starts to load it When the first byte enters the
FIFO the Tx FIFO empty interrupt will transition from active
to inactive Depending on the execution speed of the serv-
ice routine software the UART may be able to transfer this
byte from the FIFO to the shift register before the CPU
loads another byte If this happens the Tx FIFO will be emp-
ty again and typically the UART’s interrupt line would tran-
sition to the active state This could cause a system with an
interrupt control unit to record a Tx FIFO empty condition
even though the CPU is currently servicing that interrupt
Therefore after the first byte has been loaded into the FIFO
the UART will wait one serial character transmission time
before issuing a new Tx FIFO empty interrupt
This one character Tx interrupt delay will remain active until
at least two bytes have been loaded into the FIFO concur-
rently When the Tx FIFO empties after this condition the
Tx interrupt will be activated without a one character delay
Rx support functions and operation are quite different from
those described for the transmitter The Rx FIFO receives
data until the number of bytes in the FIFO equals the select-
ed interrupt trigger level At that time if Rx interrupts are
enabled the UART will issue an interrupt to the CPU The
Rx FIFO will continue to store bytes until it holds 16 of them
It will not accept any more data when it is full Any more
data entering the Rx shift register will set the Overrun Error
flag Normally the FIFO depth and the programmable trig-
ger levels will give the CPU ample time to empty the Rx
FIFO before an overrun occurs
One side-effect of having a Rx FIFO is that the selected
interrupt trigger level may be above the data level in the
FIFO This could occur when data at the end of the block
contains fewer bytes than the trigger level No interrupt
would be issued to the CPU and the data would remain in
the UART To prevent the software from having to check for
this situation the NS16550A incorporates a timeout inter-
rupt
The timeout interrupt is activated when there is at least one
byte in the Rx FIFO and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times
of the last byte The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character en-
ters it
These FIFO related features allow optimization of CPU
UART transactions and are especially useful given the high-
er baud rate capability (256 kbaud) However in order to
eliminate most CPU interactions the UART provides DMA
request signals Two DMA modes are supported single-
transfer and multi-transfer These modes allow the UART to
interface to higher performance DMA units which can inter-
leave their transfers between CPU cycles or execute multi-
ple byte transfers
In single-transfer mode the receiver DMA request signal (Rx
RDY) goes active whenever there is at least one character
in the Rx FIFO It goes inactive when the Rx FIFO is empty
The transmitter DMA request signal (Tx RDY) goes active
when there are no characters in the Tx FIFO It goes inac-
tive when there is at least one character in the Tx FIFO
Therefore in single-transfer mode active and inactive DMA
signals are issued on a one byte basis
In multi-transfer mode Rx RDY goes active whenever the
trigger level or the timeout has been reached It goes inac-
tive when the Rx FIFO is empty Tx RDY goes active when
there is at least one unfilled position in the Tx FIFO It goes
inactive when the Tx FIFO is completely full Therefore in
multi-transfer mode active and inactive DMA signals are is-
sued as the FIFO fills and empties With 2 DMA channels
(one for each Rx and Tx) assigned to it the NS16550A
could run somewhat independently of the CPU when the
DMA unit transfers data composed of blocks with check-
sums
SYSTEM OPERATION THE NS16550A VS THE NS16450
Consider the typical system interface block diagram in Fig-
ure 2 This is a simple diagram but it includes all of the
components that typically interact with a UART The advan-
tages of the NS16550A over the NS16450 can be illustrated
by comparing some of the system constraints when each
UART is substituted into this basic system
Both RS-232C and RS-422A interfaces can be used with
either UART however the NS16550A can drive these inter-
faces up to 256 kbaud Regarding the RS-422A specifica-
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FIGURE 2 Typical System Interface
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tion (max 10 Mbaud) this is significantly faster than the
NS16450 (max 56 kbaud)
The NS16450 has no DMA request signals so the DMA unit
would not interact with the NS16450 The NS16550A how-
ever has DMA request signals and two modes of data
transfer as previously described to interface with a variety
of DMA units
The greatest advantages of the NS16550A over the
NS16450 are seen when considering the CPU UART inter-
face Some characteristics of the transactions occurring be-
tween the CPU and the UART were previously cited How-
ever optimizing these transactions involves two issues
1 Decreasing the amount of time the CPU interacts with
the UART
2 Increasing the amount of data transferred between the
CPU and UART during their interaction time
These optimization criteria are directly opposed to each oth-
er but various features on the NS16550A have improved
both
One of the more obvious ways to decrease the CPU UART
interaction time is to decrease the time it takes for the trans-
action to occur The NS16550A has an access cycle time
that is almost 25% shorter than the NS16450 In addition
other timing parameters were made faster to simplify high
speed CPU interactions
The actual software required to transfer the data between
the CPU and the UART is a small percentage of that re-
quired to support this transfer However each time a trans-
fer occurs in the NS16450 this support software (overhead)
must also be executed With the NS16550A each time the
UART needs service the CPU can theoretically transfer 16
bytes while only running through its overhead once Tests
have shown that this will increase the performance by a
factor of 5 at the system level over the NS16450
Another time savings for the CPU is a new feature of the
UART interrupt structure Unlike most other UARTs with Rx
FIFOs the NS16550A will issue an interrupt when there are
characters below the interrupt trigger level after a preset
time delay This saves the extra time spent by the CPU to
check for bytes that are at the end of a block but won’t
reach the interrupt level
Since the NS16550A register set is identical to the
NS16450 on power-up all existing NS16450 software will
run on it The FIFOs are only enabled under program con-
trol
All of this added performance is not without some trade-
offs Two of the NS16450 pins no connect (NC) and chip
select out (CSOUT) have been replaced by the RxRDY and
TxRDY pins Most serial cards that currently use the
NS16450 don’t use these pins so in those situations the
NS16550A could be used as a plug-in upgrade The soft-
ware drivers for the NS16550A operating in FIFO mode
need to be a little more sophisticated than for the NS16450
This will not cause a great penalty in CPU operating time as
there is only one additional UART register to program and
one to check during the initialization One additional service
routine is required to handle Rx timeout interrupts This rou-
tine does not execute except during intermittent transmis-
sions or as described above
All of these speed improvements and allowances for soft-
ware constraints will make the NS16550A an optimal UART
for both multi-tasking systems and multiport systems Multi-
tasking systems benefit from the increased time and flexibil-
ity offered to the CPU during context switching Multiport
systems such as terminal concentrators benefit from the
on-board FIFOs and relatively autonomous functions of the
UART
SYSTEM INTERRUPT GENERATION
As a prelude to the topic of the next section (80286TM-
based system initialization) a review of a typical PC hard-
ware interrupt path is given This concerns only the interrupt
path between the UART and the CPU (see Figure 3 )
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FIGURE 3 Typical PC Interrupt System Hardware
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In order to enable interrupts from the UART to the CPU
each hardware device must be correctly initialized While
initializing the hardware path CPU interrupts are turned off
to avoid false interrupts from this path This initialization
should be as short as possible to avoid other devices
‘‘stacking up’’ interrupts during this time
After the NS16550A is initialized the bits 0–3 in the Interrupt
Enable Register (IER) are set enabling all UART interrupts
Also bit 3 in the Modem Control Register (MCR) is set to
enable the buffer between the UART and the ICU
The ICU has bit 4 of its Interrupt Mask Register (IMR)
cleared allowing interrupts occuring on IRQ4 to be trans-
ferred to the CPU via the group interrupt (INT) Finally CPU
interrupts are enabled again via the STI instruction
The programmer should be aware that the ICU will be initial-
ized for edge-triggered interrupts and that the UART always
produces level active interrupts This allows the system to
get into a situation where the UART has multiple interrupts
pending (signaled via a constantly high INTR) but the ICU
fails to respond because it expects an edge for each pend-
ing interrupt To avoid this situation the programmer should
disable all UART interrupts via the IER when entering each
UART interrupt service routine and then reenable all UART
interrupts that are to be used just before exiting each inter-
rupt service routine
SUMMARY
Up to this point the features of the NS16550A have been
described some of the design goals that resulted in these
features have been reviewed and a comparison has been
given between it and the NS16450 Increases in bus speed
and specialized functions make this part both faster from
the hardware point of view and more efficient from the soft-
ware point of view
2 0 NS16550A Initialization
This initialization can be used on any 80286-based system
it enables both FIFOs and all interrupts on the UART Addi-
tional procedures would have to be written to actually trans-
fer data and service interrupts These procedures would be
similar in form to the 32000-based example in the next sec-
tion but the code would be different The general flow of the
initialization is shown in Figure 4 and described below
DETAILED SOFTWARE DESCRIPTION
The first block in the initialization establishes abbreviations
for the NS16550A registers and assigns addresses to them
The next three blocks establish code and data segments for
the 80286 After jumping to the code start the program dis-
ables CPU interrupts (CLI) until it has finished the initializa-
tion routine Other interrupts may be active while CPU inter-
rupts are masked so the section of code following CLI
should be as short as possible The next block replaces the
existing COM1 interrupt vector with the address of
NS16550A interrupt handler (INTH in this case)
Initialization of the NS16550A is similar to the NS16450
except that there is one additional register to program which
controls the FIFOs (Refer to the datasheet for a complete
description) The sequence shown here sets bit 7 (DLAB) of
the line control register (LCR) which enables access to the
baud rate generator divisor The divisor programmed is
0006 (19 2 kbaud) in this example Programming the LCR
again resets bit 7 (allowing access to the operational regis-
ters) and programs each frame for 7 data bits one stop bit
and even parity The additional register that needs to be
programmed in the NS16550A is the FIFO control register
(FCR) The FCR data is 1100 0001 Bits 6 and 7 set the Rx
FIFO interrupt trigger level at 14 characters Bits 5 and 4 are
reserved Bit 3 keeps the DMA signal lines in mode 0 Set-
ting bits 2 and 1 clear the Tx and Rx FIFOs but this is done
automatically when the FIFOs are first enabled by setting bit
0 Bit 0 of the FCR should ALWAYS BE SET whenever
changes are to be made to the other bits of the FCR and the
UART is to remain in FIFO Mode When the FIFOs on the
NS16550A are enabled bits 6 and 7 in the Interrupt Identifi-
cation Register are set Thus the program can distinguish
between an NS16450 and an NS16550A taking advantage
of the FIFOs
Sending a 0F to the Interrupt Enable Register enables all
UART interrupts The next two register accesses reading
the Line Status Register and the Modem Status Register
are optional They are conservatively included in this initiali-
zation in order to defeat false interrupt indications in these
registers caused by noise on the external lines
The next block of code enables the interrupt signal to go
beyond the UART through the system hardware In many
popular 80286-based personal computers an interrupt con-
trol unit (ICU) has its mask register at I O address 21H To
enable interrupts through this ICU for COM1 without disturb-
ing other interrupts the Interrupt Mask Register (IMR) is
read This data is combined with 1110 1111 via an AND
instruction to unmask the COM1 interrupt and then loaded it
back to the IMR On these personal computers there is also
a buffer on the interrupt line between the UART and ICU
This buffer is enabled by setting the OUT2 bit of the MO-
DEM Control Register in the UART
Before enabling CPU interrupts (STI) pointer registers to the
data buffers of each service routine are loaded After en-
abling CPU interrupts this program jumps to a holding loop
to wait for an interrupt whereas most programs would con-
tinue initializing other devices or jump to the system loop
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FIGURE 4 NS16550A Initialization and Driver Flowchart
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