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FEATURES
38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz
Crystal
ADSP-2100 Family Code and Function Compatible with
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
2K ؋ 24 Words of On-Chip Program Memory RAM
2K ؋ 16 Words of On-Chip Data Memory RAM
4K ؋ 24 Words of On-Chip Program Memory ROM
(ADSP-21msp59 Only)
8-Bit Parallel Host Interface Port
Analog Interface Provides:
16-Bit Sigma-Delta ADC and DAC
Programmable Gain Stages
On-Chip Anti-Aliasing & Anti-Imaging Filters
8 kHz Sampling Frequency
65 dB ADC, SNR and THD
72 dB DAC, SNR and THD
425 mW Typical Power Dissipation @ 5.0 V @ 38 ns
<1 mW Powerdown Mode with 100 Cycle Recovery
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides:
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware, One Serial Port (SPORT0) has Automatic
Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (ADSP-21msp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Lead TQFP
DSP Microcomputers
ADSP-21msp58/59
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY
ADSP-21msp59
ADSP-21msp58/59
PROGRAM
MEMORY
4K x 24
(ROM)
PROGRAM DATA
MEMORY MEMORY
2K x 24
2K x 16
POWERDOWN
CONTROL
LOGIC
FLAG
ANALOG
INTERFACE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
TIMER
SERIAL PORTS
SPORT 0 SPORT 1
HOST
INTERFACE
PORT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
GENERAL DESCRIPTION
The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-
cessors (MSProcessor® DSPs) are fully integrated, single-chip
DSPs complete with a high performance analog front end. The
ADSP-21msp58/59 Family is optimized for voice band applica-
tions such as Speech Compression, Speech Processing, Speech
Recognition, Text-to Speech, and Speech-to-Text conversion.
The ADSP-21msp58/59 combines the ADSP-2100 base archi-
tecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
The ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. The ADSP-
21msp59 provides an additional 4K words (24-bit) of program
ROM. The ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. The
ADSP-21msp58/59 is available in a 100-pin TQFP package
(thin quad flat package).
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
MSProcessor is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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ADSP-21msp58/59
DIGITAL ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-21msp58/59.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; divi-
sion primitives are also supported. The MAC performs single-
cycle multiply, multiply/add, and multiply/subtract operations.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The shifter
can be used to efficiently implement numeric format control in-
cluding multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21msp58/59 executes looped code with
zero overhead—no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for si-
multaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four
modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for circular
buffers. The circular buffering feature is also used by the serial
ports for automatic data transfers to (and from) on-chip
memory.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA, DMA) share a single external ad-
dress bus, allowing memory to be expanded off chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space the external buses are being used for.
Program memory can store both instructions and data, permit-
ting the ADSP-21msp58/59 to fetch two operands in a single
cycle, one from program memory and one from data memory.
The ADSP-21msp58/59 can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processors’ buses with
the use of the bus request/grant signals (BR and BG). Bus grant
has two modes of operation. If GoMode is enabled in the MSTAT
register, instruction execution continues from internal memory.
If GoMode is disabled, the processor stops instruction execution
and waits for deassertion of BR.
In addition to the address and data bus for external memory
connection, the ADSP-21msp58/59 has a host interface port
(HIP) for easy connection to a host processor. The HIP is made
up of 8 data/address pins and 10 control pins. The HIP is ex-
tremely flexible and provides a simple interface to a variety of
host processors. For example, the Motorola 68000 series, the
Intel 80C51 series, and the Analog Devices ADSP-2101 can be
easily connected to the HIP. The host processor can boot the
ADSP-21msp58/59 on-chip memory through the HIP.
The ADSP-21msp58/59 can respond to eleven interrupts. There
can be up to three external interrupts, configured as edge- or
level-sensitive, and seven internal interrupts generated by the
Timer, the Serial Ports (SPORTs), the HIP, the powerdown cir-
cuitry, and the analog interface. There is also a master RESET
signal.
The two serial ports provide a complete synchronous serial in-
terface with optional companding in hardware and a wide vari-
ety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable se-
rial clock or accept an external serial clock.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
PROGRAM
SRAM
2K x 24
PROGRAM
ROM
4K x 24
(ADSP-21msp59)
14 PMA BUS
14 DMA BUS
24 PMD BUS
16 DMD BUS
DATA
SRAM
2K x 16
BOOT
ADDRESS
GENERATOR
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
INPUT REGS
SHIFTER
OUTPUT REGS
16 R BUS
CONTROL
LOGIC
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
55
TIMER
Figure 1. ADSP-21msp58/59 Block Diagram
FLAG
ADC, DAC
AND
FILTERS
1
7
MUX
14
MUX
24
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
HIP
CONTROL
10
HIP
REGISTER
8
POWER
DOWN
CONTROL
LOGIC
1
HIP
DATA
BUS
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ADSP-21msp58/59
seven wait states are automatically generated. This allows, for
example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM
as external boot memory. Multiple programs can be selected
and loaded from the EPROM with no additional hardware. The
on-chip program memory can also be initialized through the
HIP.
The ADSP-21msp58/59 features a general purpose flag output
whose state is controlled through software. You can use this
output to signal an event to an external device. In addition, the
data input and output pins on SPORT1 can be alternatively
configured as an input and an output flag.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
The ADSP-21msp58/59 instruction set provides flexible data
moves and multifunction (one or two data moves with a compu-
tation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-21msp58/59 uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Serial Ports
The ADSP-21msp58/59 processors include two synchronous se-
rial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-21msp58/59
SPORTs. Refer to the ADSP-2100 Family User’s Manual for fur-
ther details.
• SPORTs are bidirectional with a separate, double-buffered
transmit and receive section.
• SPORTs can use an external serial clock or generate their own
clock internally.
• SPORTs have independent framing for the transmit and
receive sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gener-
ated. Frame sync signals are programmed to be active high or
low, with either of two pulse widths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORTs receive and transmit sections generate separate
interrupts when the SPORTs are ready to read or write new
data.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word (Autobuffering
Mode). An interrupt is generated after a complete data buffer
transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed
serial bit stream.
• SPORT1 can be reconfigured as two external interrupt inputs
(IRQ0 and IRQ1) and the Flag In and Flag Out signals (FI,
FO). The internally generated serial clock may still be used in
this configuration.
Pin Descriptions
The ADSP-21msp58 and ADSP-21msp59 are available in a
100-lead TQFP package. Table I contains the pin descriptions.
Table I. ADSP-21msp58/59 Pin List
Pin
Group
Name
#
of Input/
Pins Output Function
Digital Pins
Address
14 O
Data
24 I/O
RESET
IRQ2
BR
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN,
XTAL
1
1
1
1
1
1
1
1
1
1
2
CLKOUT
HACK
HSEL
BMODE
1
1
1
1
I
I
I
O
O
O
O
O
O
I
I
O
O
I
I
HMD0
1
HMD1
1
HRD/HRW 1
HWR/HDS 1
HD7–0/
HAD7–0
8
HA2/ALE 1
HA1–0/
(unused)
SPORT0
2
5
SPORT1 5
or
I
I
I
I
I/O
I
I
I/O
I/O
Address output for program,
data and boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
External clock or quartz crystal
input
Processor clock output
HIP acknowledge output
HIP select input
Boot mode select (0 = Standard
EPROM Booting, 1 = HIP
Booting)
Bus strobe select (0 = RD/WR,
1 = RW/DS)
HIP address/data mode select
(0 = Separate, 1 = Multiplexed)
HIP read strobe or read/write
select
HIP write strobe or host data
strobe select
HIP data or HIP data and
address
Host address 2 or address latch
enable
Host address 1 and 0 inputs
Serial port 0 pins (TFS0, RFS0,
DT0, DR0, SCLK0)
Serial port 1 pins (TFS1, RFS1,
DT1, DR1, SCLK1)
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ADSP-21msp58/59
Pin
Group
Name
#
of Input/
Pins Output Function
IRQ0 (RFS1) 1
IRQ1 (TFS1) 1
SCLK1
1
FI (DR1) 1
FO (DT1) 1
FL0 1
VDD
GND
4
5
PWD
1
Analog Pins
VINNORM
1
I
I
O
I
O
O
I
I
VINAUX
1I
Decouple 1 I
VOUTP
1O
VOUTN
1O
VREF
REF_
FILTER
VCC
GNDA
1O
1O
1
2
External interrupt request #0
External interrupt request #1
Programmable clock output
Flag input pin
Flag output pin
General purpose flag output pin
Digital power supply pins
Ground pins
Powerdown pin
Input terminal of the NORM
amplifier for the encoder section
(ADC)
Input terminal of the AUX
amplifier for the encoder section
(ADC)
Ground reference of the NORM
and AUX amplifiers for the
encoder section (ADC)
Noninverting output terminal of
the differential amplifier from
the decoder section (DAC)
Inverting output terminal of the
differential amplifier from the
decoder section (DAC)
Output voltage reference
Voltage reference external by-
pass filter node
Analog power supply
Analog ground
Host Interface Port
The ADSP-21msp58/59 host interface port (HIP) is a parallel
I/O port that allows for an easy connection to a host processor.
Through the HIP, the ADSP-21msp58/59 can be used as a
memory-mapped peripheral to a host computer. The HIP can
be thought of as an area of dual-ported memory, or mailbox reg-
isters, that allows communication between the computational
core of the ADSP-21msp58/59 and the host computer.
The host interface port is completely asynchronous. The host
processor can write data into the HIP while the ADSP-
21msp58/59 is operating at full speed.
The HIP can be configured with the following pins:
• BMODE (when MMAP = 0) determines whether the ADSP-
21msp58/59 boots from the host processor (through the HIP)
or external EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (8-bit) buses,
or a multiplexed 8-bit address/data bus with address latch
enable.
Tying these pins to appropriate values configures the ADSP-
21msp58/59 for straight-wire interface to a variety of industry-
standard microprocessors and microcomputers.
When the host processor writes an 8-bit value to the HIP, the
upper eight bits of the HIP registers are all zeros. For additional
information, refer to the ADSP-2100 Family User’s Manual,
Chapter 7, for information about 8-bit configuration.
HIP Operation
The HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. The HIP
data registers are memory-mapped in the internal data memory
of the ADSP-21msp58/59. HIP transfers can be managed using
either interrupts or polling. These registers are shown in the sec-
tion “ADSP-21msp58/59 Registers.” The two status registers
provide status information to both the ADSP-21msp58/59 and
the host processor. HSR7 contains a software reset bit that can
be set by the ADSP-21msp58/59 and the host.
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-21msp58/59 cycles.
The HIP generates an interrupt whenever an HDR register re-
ceives data from a host processor write. It also generates an in-
terrupt when the host processor has performed a successful read
of any HDR. The read/write status of the HDRs is also stored in
the HSR registers.
The HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.
The HIP provides a second method of booting the ADSP-
21msp58/59 in which the host processor loads instructions into
the HIP. The ADSP-21msp58/59 automatically transfers the
data, in this case opcodes, to internal program memory. The
BMODE pin determines whether the ADSP-21msp58/59 boots
from the host processor through the HIP or from external
EPROM over the data bus.
Interrupts
The interrupt controller lets the processor respond to interrupts
and reset with a minimum of overhead. The ADSP-21msp58/59
provides up to three external interrupt input pins, IRQ0, IRQ1,
and IRQ2. IRQ2 is always available as a dedicated pin;
SPORT1 may be reconfigured for IRQ1 and IRQ0 and the flag.
The ADSP-21msp58/59 also supports internal interrupts from
the timer, the host interface port, the serial ports, the analog in-
terface, and the powerdown control circuit. The interrupts are
internally prioritized and individually maskable (except for
powerdown and RESET). The input pins can be programmed
for either level- or edge-sensitivity. The priorities and vector ad-
dresses for the interrupts are shown in Table II; the interrupt
registers are shown in Figure 2.
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ADSP-21msp58/59
ICNTL
4 3210
0
IMASK
98765 4 3210
0000000000
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
1 = edge
0 = level
Interrupt Nesting
1 = enable, 0 = disable
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Analog Receive
Analog Transmit
1 = enable, 0 = disable
INTERRUPT FORCE
IRQ2
SPORT0 Transmit
SPORT0 Receive
Analog Transmit
Analog Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT CLEAR
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Analog Receive
Analog Transmit
SPORT0 Receive
SPORT0 Transmit
IRQ2
1 = enable, 0 = disable
Figure 2. Interrupt Registers
Table II. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Analog Interface Transmit
Analog Interface Receive
SPORT1 Transmit or (IRQ1)
SPORT1 Receive or (IRQ0)
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected. The powerdown interrupt is non-maskable.
The interrupt control register, ICNTL, allows the external in-
terrupts to be set as either edge- or level-sensitive. Interrupt ser-
vice routines can either be nested (with higher priority interrupts
taking precedence) or be processed sequentially (with only one
interrupt service active at a time).
The interrupt force and clear register, IFC, is a write-only regis-
ter used to force an interrupt or clear a pending edge-sensitive
interrupt.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stack is twelve
levels deep to allow interrupt nesting.
Register bit values shown in Figure 2 are the default bit values
after reset. If no values are shown, the bits are indeterminate at
reset. Reserved bits are shown in gray; these bits should always
be written with zeros.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
Interrupt servicing is enabled on processor reset.
System Interface
Figure 3 shows a basic system configuration with the ADSP-
21msp58/59, two serial devices, a host processor, a boot
EPROM, optional external program and data memories, and an
analog interface. Up to 15K words of data memory and 16K
words of program memory can be supported. Programmable
wait state generation allows the processor to interface easily to
slow memories. The ADSP-21msp58/59 also provides one ex-
ternal interrupt and two serial ports or three external interrupts
and one serial port.
Clock Signals
The ADSP-21msp58/59 CLKIN input may be driven by a crys-
tal or by a TTL-compatible external clock signal.
The CLKIN input may not be halted, changed in frequency
during operation, or operated at any frequency other the one
specified. Operating the ADSP-21msp58/59 at any other fre-
quency changes the analog performance, which is not tested or
supported.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
The ADSP-21msp58/59 uses an input clock with a frequency
equal to half the instruction rate; a 13 MHz input clock yields a
38.46 ns processor cycle (which is equivalent to 26 MHz). Nor-
mally, instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled. The
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