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8XC196MC
INDUSTRIAL MOTOR CONTROL
MICROCONTROLLER
87C196MC 16 Kbytes of On-Chip OTPROM
87C196MC ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM
80C196MC ROMless
Y High-Performance CHMOS 16-Bit CPU
Y 16 Kbytes of On-Chip OTPROM
Factory-Programmed OTPROM
Y 488 bytes of On-Chip Register RAM
Y Register to Register Architecture
Y Up to 53 I O Lines
Y Peripheral Transaction Server (PTS)
with 11 Prioritized Sources
Y Event Processor Array (EPA)
4 High Speed Capture Compare
Modules
4 High Speed Compare Modules
Y Extended Temperature Standard
Y Two 16-Bit Timers with Quadrature
Decoder Input
Y 3-Phase Complementary Waveform
Generator
Y 13 Channel 8 10-Bit A D with Sample
Hold with Zero Offset Adjustment H W
Y 14 Prioritized Interrupt Sources
Y Flexible 8- 16-Bit External Bus
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y Idle and Power Down Modes
The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors The 8XC196MC is based on Intel’s MCS 96 16-bit microcontroller architecture and is manufac-
tured with Intel’s CHMOS process
The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications This peripheral allows for pulse width modulation three phase sine wave generation with
minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of
0 125 ms (edge trigger) or 0 250 ms (centered)
The 8XC196MC has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in three
packages PLCC (84-L) SDIP (64-L) and EIAJ QFP (80-L)
Note that the 64-L SDIP package does not include P1 4 P2 7 P5 1 and the CLKOUT pins
Operational characteristics are guaranteed over the temperature range of b40 C to a85 C
The 87C196MC contains 16 Kbytes on-chip OTPROM The 83C196MC contains 16 Kbytes on-chip ROM All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted
OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased It is user programmable
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
April 1994
Order Number 270946-005

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8XC196MC
NOTE
Connections between the standard I O ports and the bus are not shown
Figure 1 87C196MC Block Diagram
270946 – 1
2

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8XC196MC
PROCESS INFORMATION
This device is manufactured on PX29 5 a CHMOS
III-E process Additional process and reliability infor-
mation is available in Intel’s Components Quality
and Reliability Handbook Order Number 210997
270946 – 16
EXAMPLE N87C196MC is 84-Lead PLCC OTPROM
16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)
NOTE
1 EPROMs are available as One Time Programmable
(OTPROM) only
Figure 3 The 8XC196MC Family Nomenclature
Thermal Characteristics
Package
Type
ija
ijc
PLCC
35 C W
13 C W
QFP
56 C W
12 C W
SDIP
TBD
TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology
8XC196MC Memory Map
Description
Address
External Memory or I O
0FFFFH
06000H
Internal ROM EPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved Must contain FFH
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM EPROM Security Key
202FH
2020H
Reserved Must contain FFH
(Note 5)
201FH
201CH
Reserved Must Contain 20H
(Note 5)
201BH
CCB1
201AH
Reserved Must Contain 20H
(Note 5)
2019H
CCB0
2018H
Reserved Must contain FFH
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
SFR’s
1FFFH
1F00H
External Memory
1EFFH
0200H
488 Bytes Register RAM (Note 1)
01FFH
0018H
CPU SFR’s (Notes 1 3)
0017H
0000H
NOTES
1 Code executed in locations 0000H to 03FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196KC for SFR descriptions
5 WARNING Reserved memory locations must not be
written or read The contents and or function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
locations may not function properly
3